my_sram_translate.vhd

FPGA系统的sram的软仿真设计

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim my_sram.ngd my_sram_translate.vhd 
-- Input file    : my_sram.ngd
-- Output file   : my_sram_translate.vhd
-- Design name   : my_sram
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 2s15cs144-6

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity my_sram is
  port (
    re : in STD_LOGIC := 'X'; 
    clock : in STD_LOGIC := 'X'; 
    we : in STD_LOGIC := 'X'; 
    data_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    raddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    waddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    data_out : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end my_sram;

architecture Structure of my_sram is
  signal re_IBUF : STD_LOGIC; 
  signal clock_BUFGP : STD_LOGIC; 
  signal we_IBUF : STD_LOGIC; 
  signal data_7_0 : STD_LOGIC; 
  signal data_0_4 : STD_LOGIC; 
  signal data_0_2 : STD_LOGIC; 
  signal data_0_0 : STD_LOGIC; 
  signal data_5_2 : STD_LOGIC; 
  signal data_5_4 : STD_LOGIC; 
  signal data_5_1 : STD_LOGIC; 
  signal data_7_2 : STD_LOGIC; 
  signal Q_n0019 : STD_LOGIC; 
  signal Q_n0031 : STD_LOGIC; 
  signal data_5_0 : STD_LOGIC; 
  signal data_0_6 : STD_LOGIC; 
  signal data_0_7 : STD_LOGIC; 
  signal data_1_0 : STD_LOGIC; 
  signal Q_n0040 : STD_LOGIC; 
  signal data_1_1 : STD_LOGIC; 
  signal data_0_5 : STD_LOGIC; 
  signal data_1_2 : STD_LOGIC; 
  signal data_7_7 : STD_LOGIC; 
  signal data_1_3 : STD_LOGIC; 
  signal data_0_3 : STD_LOGIC; 
  signal data_1_4 : STD_LOGIC; 
  signal Q_n0044 : STD_LOGIC; 
  signal data_1_5 : STD_LOGIC; 
  signal Q_n0050 : STD_LOGIC; 
  signal data_0_1 : STD_LOGIC; 
  signal data_7_3 : STD_LOGIC; 
  signal Q_n0046 : STD_LOGIC; 
  signal Q_n0052 : STD_LOGIC; 
  signal data_5_3 : STD_LOGIC; 
  signal data_7_1 : STD_LOGIC; 
  signal Q_n0048 : STD_LOGIC; 
  signal Q_n0054 : STD_LOGIC; 
  signal data_7_5 : STD_LOGIC; 
  signal data_5_7 : STD_LOGIC; 
  signal data_7_6 : STD_LOGIC; 
  signal Q_n0056 : STD_LOGIC; 
  signal data_5_6 : STD_LOGIC; 
  signal data_7_4 : STD_LOGIC; 
  signal data_5_5 : STD_LOGIC; 
  signal data_out_7 : STD_LOGIC; 
  signal data_out_6 : STD_LOGIC; 
  signal data_out_5 : STD_LOGIC; 
  signal data_out_4 : STD_LOGIC; 
  signal data_out_3 : STD_LOGIC; 
  signal data_out_2 : STD_LOGIC; 
  signal data_out_1 : STD_LOGIC; 
  signal data_out_0 : STD_LOGIC; 
  signal data_in_7_IBUF : STD_LOGIC; 
  signal data_in_6_IBUF : STD_LOGIC; 
  signal data_in_5_IBUF : STD_LOGIC; 
  signal data_in_4_IBUF : STD_LOGIC; 
  signal data_in_3_IBUF : STD_LOGIC; 
  signal data_in_2_IBUF : STD_LOGIC; 
  signal data_in_1_IBUF : STD_LOGIC; 
  signal data_in_0_IBUF : STD_LOGIC; 
  signal raddr_2_IBUF : STD_LOGIC; 
  signal raddr_1_IBUF : STD_LOGIC; 
  signal raddr_0_IBUF : STD_LOGIC; 
  signal waddr_2_IBUF : STD_LOGIC; 
  signal waddr_1_IBUF : STD_LOGIC; 
  signal waddr_0_IBUF : STD_LOGIC; 
  signal data_2_6 : STD_LOGIC; 
  signal data_2_7 : STD_LOGIC; 
  signal data_6_5 : STD_LOGIC; 
  signal data_6_4 : STD_LOGIC; 
  signal data_6_3 : STD_LOGIC; 
  signal data_6_2 : STD_LOGIC; 
  signal data_6_1 : STD_LOGIC; 
  signal data_6_0 : STD_LOGIC; 
  signal data_1_6 : STD_LOGIC; 
  signal data_1_7 : STD_LOGIC; 
  signal data_2_0 : STD_LOGIC; 
  signal data_2_1 : STD_LOGIC; 
  signal data_2_2 : STD_LOGIC; 
  signal data_2_3 : STD_LOGIC; 
  signal data_2_4 : STD_LOGIC; 
  signal data_2_5 : STD_LOGIC; 
  signal data_3_6 : STD_LOGIC; 
  signal data_3_7 : STD_LOGIC; 
  signal data_4_0 : STD_LOGIC; 
  signal data_4_1 : STD_LOGIC; 
  signal data_4_2 : STD_LOGIC; 
  signal data_4_3 : STD_LOGIC; 
  signal data_4_4 : STD_LOGIC; 
  signal data_4_5 : STD_LOGIC; 
  signal data_4_6 : STD_LOGIC; 
  signal data_4_7 : STD_LOGIC; 
  signal data_6_6 : STD_LOGIC; 
  signal data_6_7 : STD_LOGIC; 
  signal data_3_0 : STD_LOGIC; 
  signal data_3_1 : STD_LOGIC; 
  signal data_3_2 : STD_LOGIC; 
  signal data_3_3 : STD_LOGIC; 
  signal data_3_4 : STD_LOGIC; 
  signal data_3_5 : STD_LOGIC; 
  signal Mmux_n0011_net7 : STD_LOGIC; 
  signal Mmux_n0011_net0 : STD_LOGIC; 
  signal Mmux_n0011_net1 : STD_LOGIC; 
  signal Mmux_n0011_net2 : STD_LOGIC; 
  signal Mmux_n0011_net3 : STD_LOGIC; 
  signal Mmux_n0011_net4 : STD_LOGIC; 
  signal Mmux_n0011_net5 : STD_LOGIC; 
  signal Mmux_n0011_net54 : STD_LOGIC; 
  signal Mmux_n0011_net53 : STD_LOGIC; 
  signal Mmux_n0011_net52 : STD_LOGIC; 
  signal Mmux_n0011_net51 : STD_LOGIC; 
  signal Mmux_n0011_net50 : STD_LOGIC; 
  signal Mmux_n0011_net49 : STD_LOGIC; 
  signal Mmux_n0011_net47 : STD_LOGIC; 
  signal Mmux_n0011_net46 : STD_LOGIC; 
  signal Mmux_n0011_net45 : STD_LOGIC; 
  signal Mmux_n0011_net44 : STD_LOGIC; 
  signal Mmux_n0011_net43 : STD_LOGIC; 
  signal Mmux_n0011_net42 : STD_LOGIC; 
  signal Mmux_n0011_net40 : STD_LOGIC; 
  signal Mmux_n0011_net39 : STD_LOGIC; 
  signal Mmux_n0011_net38 : STD_LOGIC; 
  signal Mmux_n0011_net37 : STD_LOGIC; 
  signal Mmux_n0011_net36 : STD_LOGIC; 
  signal Mmux_n0011_net35 : STD_LOGIC; 
  signal Mmux_n0011_net33 : STD_LOGIC; 
  signal Mmux_n0011_net32 : STD_LOGIC; 
  signal Mmux_n0011_net31 : STD_LOGIC; 
  signal Mmux_n0011_net30 : STD_LOGIC; 
  signal Mmux_n0011_net29 : STD_LOGIC; 
  signal Mmux_n0011_net28 : STD_LOGIC; 
  signal Mmux_n0011_net26 : STD_LOGIC; 
  signal Mmux_n0011_net25 : STD_LOGIC; 
  signal Mmux_n0011_net24 : STD_LOGIC; 
  signal Mmux_n0011_net23 : STD_LOGIC; 
  signal Mmux_n0011_net22 : STD_LOGIC; 
  signal Mmux_n0011_net21 : STD_LOGIC; 
  signal Mmux_n0011_net19 : STD_LOGIC; 
  signal Mmux_n0011_net18 : STD_LOGIC; 
  signal Mmux_n0011_net17 : STD_LOGIC; 
  signal Mmux_n0011_net16 : STD_LOGIC; 
  signal Mmux_n0011_net15 : STD_LOGIC; 
  signal Mmux_n0011_net14 : STD_LOGIC; 
  signal Mmux_n0011_net12 : STD_LOGIC; 
  signal Mmux_n0011_net11 : STD_LOGIC; 
  signal Mmux_n0011_net10 : STD_LOGIC; 
  signal Mmux_n0011_net9 : STD_LOGIC; 
  signal Mmux_n0011_net8 : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_311_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_301_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_291_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_281_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_271_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_261_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_251_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_241_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_231_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_221_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_211_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_201_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_191_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_181_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_171_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_161_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_151_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_141_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_131_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_121_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_111_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_101_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_91_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_81_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_71_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_61_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_51_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_41_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_32_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_210_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_110_O : STD_LOGIC; 
  signal Mmux_n0011_inst_lut3_01_O : STD_LOGIC; 
  signal Mmux_n0002_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_6_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_5_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_4_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_3_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_2_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_1_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_0_1_O : STD_LOGIC; 
  signal Mmux_n0002_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0003_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0004_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0005_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0006_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0007_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0008_Result_7_1_O : STD_LOGIC; 
  signal Mmux_n0009_Result_7_1_O : STD_LOGIC; 
  signal clock_BUFGP_IBUFG : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal data_out_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal data_out_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_7_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal data_out_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_data_out_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_7_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_data_out_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal Q_n0011 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0006 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0002 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0005 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0009 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0004 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0008 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0007 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0003 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  Q_n00561 : X_LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => waddr_1_IBUF,
      ADR2 => waddr_2_IBUF,
      O => Q_n0056
    );
  Q_n00541 : X_LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_0_IBUF,
      O => Q_n0054
    );
  Q_n00521 : X_LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_0_IBUF,
      O => Q_n0052
    );
  Q_n00501 : X_LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => waddr_1_IBUF,
      ADR2 => waddr_0_IBUF,
      O => Q_n0050
    );
  Q_n00481 : X_LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => waddr_1_IBUF,
      ADR2 => waddr_0_IBUF,
      O => Q_n0048
    );
  Q_n00461 : X_LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => waddr_0_IBUF,
      ADR2 => waddr_1_IBUF,
      O => Q_n0046
    );
  Q_n00441 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => waddr_1_IBUF,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_0_IBUF,
      O => Q_n0044
    );
  Q_n00401 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => we_IBUF,
      ADR1 => re_IBUF,
      O => Q_n0040
    );
  Q_n00311 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => re_IBUF,
      ADR1 => we_IBUF,
      O => Q_n0031
    );
  data_1_6_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_6,
      SET => GND,
      RST => GSR
    );
  data_1_5_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_5,
      SET => GND,
      RST => GSR
    );
  data_1_3_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_3,
      SET => GND,
      RST => GSR
    );
  data_1_4_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_4,
      SET => GND,
      RST => GSR
    );
  data_0_6_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(6),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_6,
      SET => GND,
      RST => GSR
    );
  data_0_5_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(5),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_5,
      SET => GND,
      RST => GSR
    );
  data_0_4_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(4),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_4,
      SET => GND,
      RST => GSR
    );
  data_0_3_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(3),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_3,
      SET => GND,
      RST => GSR
    );
  data_0_2_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(2),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_2,
      SET => GND,
      RST => GSR
    );
  data_0_1_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(1),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_1,
      SET => GND,
      RST => GSR
    );
  data_0_0_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(0),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_0,
      SET => GND,
      RST => GSR
    );
  Q_n00191 : X_LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => waddr_0_IBUF,
      ADR2 => waddr_1_IBUF,
      O => Q_n0019
    );
  data_1_7_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_1_7,
      SET => GND,
      RST => GSR
    );
  data_0_7_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(7),
      CE => Q_n0031,
      CLK => clock_BUFGP,
      O => data_0_7,
      SET => GND,
      RST => GSR
    );
  Mmux_n0011_inst_mux_f6_7 : X_MUX2
    port map (
      IA => Mmux_n0011_net51,
      IB => Mmux_n0011_net54,
      SEL => raddr_2_IBUF,
      O => Q_n0011(7)
    );
  data_2_7_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0004(7),