my_sram.vhd

FPGA系统的sram的软仿真设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity my_sram is
    Port ( data_in : in std_logic_vector(7 downto 0);
    		 cs : in std_logic;
           we : in std_logic;
           re : in std_logic;
           clk : in std_logic;
           waddr : in std_logic_vector(2 downto 0);
           raddr : in std_logic_vector(2 downto 0);
           data_out : out std_logic_vector(7 downto 0));
end my_sram;


architecture Behavioral of my_sram is
				    
type memtype is array(0 to 7) of std_logic_vector(7 downto	0);
signal mem: memtype;
signal waddrmix : std_logic_vector(2 downto 0);
signal raddrmix : std_logic_vector(2 downto 0);
begin
waddrmix <= waddr;
raddrmix <= raddr;			   
	process(clk,cs)
     begin
	if(cs = '1')then
		if ( clk'event and clk = '1') then
			if(we = '1')then
				mem(CONV_INTEGER(waddrmix)) <= data_in;
			end if;

			if(re = '1')then 
				data_out <= mem(CONV_INTEGER(raddrmix));
			else
				data_out <= (others => 'Z');
			end if;

		end if;
	else
		data_out <= (others => 'Z');
	end if;
	end process;

end Behavioral;