my_sram.par

FPGA系统的sram的软仿真设计

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

WENGERM::  Wed May 30 01:42:55 2007


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 my_sram_map.ncd
my_sram.ncd my_sram.pcf 


Constraints file: my_sram.pcf

Loading device database for application Par from file "my_sram_map.ncd".
   "my_sram" is an NCD, version 2.38, device xc2s15, package cs144, speed -6
Loading device for application Par from file '2s15.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            25 out of 86     29%
      Number of LOCed External IOBs    0 out of 25      0%

   Number of SLICEs                   50 out of 192    26%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897d8) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
....
Phase 5.8 (Checksum:9a0b27) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file my_sram.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 321 unrouted;       REAL time: 0 secs 

Phase 2: 276 unrouted;       REAL time: 0 secs 

Phase 3: 62 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   45   |  0.051     |  0.365      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 164


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.227
   The MAXIMUM PIN DELAY IS:                               4.135
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.047

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         115         175          23           6           2           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  44 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file my_sram.ncd.


PAR done.