sram.syr

FPGA系统的sram的软仿真设计

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: sram.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sram.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sram
Output Format                      : NGC
Target Device                      : xc2s15-6-cs144

---- Source Options
Top Module Name                    : sram
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sram.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/MyFPGA/sram2.vhd in Library work.
Architecture behaviour of Entity sram is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sram> (Architecture <behaviour>).
WARNING:Xst:790 - G:/MyFPGA/sram2.vhd line 47: Index value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <mem> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
WARNING:Xst:790 - G:/MyFPGA/sram2.vhd line 57: Index value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <mem> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Entity <sram> analyzed. Unit <sram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sram>.
    Related source file is G:/MyFPGA/sram2.vhd.
    Found 65536x32-bit single-port distributed RAM for signal <mem>.
    -----------------------------------------------------------------------
    | aspect ratio       | 65536-word x 32-bit                 |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to internal node          | high     |
    | address            | connected to signal <address<15:0>> |          |
    | data in            | connected to signal <data>          |          |
    | data out           | connected to internal node          |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:1772 - You have explicitly defined initial contents for this RAM, which are currently ignored when the RAM is implemented with LUT resources, leading to incorrect circuit behavior. Changing the RAM description so that it is read synchronously will allow implementation on block RAM resources for which we provide full initial contents support.
    Found 32-bit tristate buffer for signal <data>.
    Found 18-bit comparator less for signal <$n0039> created at line 46.
    Found 3-bit shift register for signal <bus_tri>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Comparator(s).
	inferred  32 Shift register(s).
	inferred  32 Tristate(s).
Unit <sram> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 1
 65536x32-bit single-port distributed RAM: 1
# Shift Registers                  : 32
 3-bit shift register              : 32
# Comparators                      : 1
 18-bit comparator less            : 1
# Tristates                        : 1
 32-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================