my_sram.twr

FPGA系统的sram的软仿真设计

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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml my_sram my_sram.ncd -o
my_sram.twr my_sram.pcf


Design file:              my_sram.ncd
Physical constraint file: my_sram.pcf
Device,speed:             xc2s15,-6 (PRODUCTION 1.27 2004-06-25)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
cs          |    5.052(R)|   -2.322(R)|clk_BUFGP         |   0.000|
data_in<0>  |    2.083(R)|   -0.291(R)|clk_BUFGP         |   0.000|
data_in<1>  |    2.083(R)|   -0.299(R)|clk_BUFGP         |   0.000|
data_in<2>  |    2.083(R)|   -0.326(R)|clk_BUFGP         |   0.000|
data_in<3>  |    2.083(R)|   -0.249(R)|clk_BUFGP         |   0.000|
data_in<4>  |    2.104(R)|   -0.640(R)|clk_BUFGP         |   0.000|
data_in<5>  |    2.104(R)|   -0.598(R)|clk_BUFGP         |   0.000|
data_in<6>  |    2.104(R)|   -0.577(R)|clk_BUFGP         |   0.000|
data_in<7>  |    2.104(R)|   -0.445(R)|clk_BUFGP         |   0.000|
raddr<0>    |    4.834(R)|   -3.123(R)|clk_BUFGP         |   0.000|
raddr<1>    |    5.294(R)|   -2.896(R)|clk_BUFGP         |   0.000|
raddr<2>    |    4.262(R)|   -2.762(R)|clk_BUFGP         |   0.000|
re          |    0.758(R)|    0.024(R)|clk_BUFGP         |   0.000|
waddr<0>    |    3.931(R)|   -1.662(R)|clk_BUFGP         |   0.000|
waddr<1>    |    4.789(R)|   -2.059(R)|clk_BUFGP         |   0.000|
waddr<2>    |    3.525(R)|   -1.467(R)|clk_BUFGP         |   0.000|
we          |    5.052(R)|   -2.114(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
data_out<0> |    6.804(R)|clk_BUFGP         |   0.000|
data_out<1> |    6.773(R)|clk_BUFGP         |   0.000|
data_out<2> |    6.804(R)|clk_BUFGP         |   0.000|
data_out<3> |    6.804(R)|clk_BUFGP         |   0.000|
data_out<4> |    6.804(R)|clk_BUFGP         |   0.000|
data_out<5> |    6.783(R)|clk_BUFGP         |   0.000|
data_out<6> |    6.783(R)|clk_BUFGP         |   0.000|
data_out<7> |    6.753(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.343|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed May 30 01:42:57 2007
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Peak Memory Usage: 42 MB