myfpga.npl

FPGA系统的sram的软仿真设计

JDF G
// Created by Project Navigator ver 1.0
PROJECT MyFPGA
DESIGN myfpga
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s15
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE my_sram.vhd
[STATUS-ALL]
my_sram.ncdFile=WARNINGS,1180460575
[STRATEGY-LIST]
Normal=True