my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

      RST => data_in_1_IFF_RST,
      O => mem_7_1
    );
  data_in_1_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_1_IFF_RST
    );
  Mtridata_data_out_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_6_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_6_OFF_RST,
      O => Mtridata_data_out(6)
    );
  data_out_6_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_6_OFF_RST
    );
  mem_3_3_76 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_3_3_FFX_RST,
      O => mem_3_3
    );
  mem_3_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_3_3_FFX_RST
    );
  mem_3_4_77 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_3_5_FFY_RST,
      O => mem_3_4
    );
  mem_3_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_3_5_FFY_RST
    );
  mem_3_5_78 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_3_5_FFX_RST,
      O => mem_3_5
    );
  mem_3_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_3_5_FFX_RST
    );
  mem_4_0_79 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_1_FFY_RST,
      O => mem_4_0
    );
  mem_4_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_1_FFY_RST
    );
  mem_4_1_80 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_1_FFX_RST,
      O => mem_4_1
    );
  mem_4_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_1_FFX_RST
    );
  mem_3_6_81 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_3_7_FFY_RST,
      O => mem_3_6
    );
  mem_3_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_3_7_FFY_RST
    );
  mem_3_7_82 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_3_7_FFX_RST,
      O => mem_3_7
    );
  mem_3_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_3_7_FFX_RST
    );
  mem_4_2_83 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_3_FFY_RST,
      O => mem_4_2
    );
  mem_4_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_3_FFY_RST
    );
  mem_4_3_84 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_3_FFX_RST,
      O => mem_4_3
    );
  mem_4_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_3_FFX_RST
    );
  mem_4_4_85 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_5_FFY_RST,
      O => mem_4_4
    );
  mem_4_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_5_FFY_RST
    );
  mem_4_5_86 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_5_FFX_RST,
      O => mem_4_5
    );
  mem_4_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_5_FFX_RST
    );
  mem_4_6_87 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_7_FFY_RST,
      O => mem_4_6
    );
  mem_4_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_7_FFY_RST
    );
  mem_5_0_88 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_1_FFY_RST,
      O => mem_5_0
    );
  mem_5_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_1_FFY_RST
    );
  mem_5_1_89 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_1_FFX_RST,
      O => mem_5_1
    );
  mem_5_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_1_FFX_RST
    );
  Mtrien_data_out_2_90 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_6_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_6_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_1
    );
  data_out_6_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_6_SRMUXNOT,
      O => data_out_6_TFF_SET
    );
  mem_7_2_91 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IDELAY,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_2_IFF_RST,
      O => mem_7_2
    );
  data_in_2_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_2_IFF_RST
    );
  Mtridata_data_out_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_7_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_7_OFF_RST,
      O => Mtridata_data_out(7)
    );
  data_out_7_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_7_OFF_RST
    );
  Mtrien_data_out_1_92 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_7_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_7_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_0
    );
  data_out_7_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_7_SRMUXNOT,
      O => data_out_7_TFF_SET
    );
  mem_7_3_93 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IDELAY,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_3_IFF_RST,
      O => mem_7_3
    );
  data_in_3_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_3_IFF_RST
    );
  mem_0_4_94 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IDELAY,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_4_IFF_RST,
      O => mem_0_4
    );
  data_in_4_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_4_IFF_RST
    );
  mem_0_5_95 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IDELAY,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_5_IFF_RST,
      O => mem_0_5
    );
  data_in_5_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_5_IFF_RST
    );
  mem_1_4_96 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_5_FFY_RST,
      O => mem_1_4
    );
  mem_1_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_5_FFY_RST
    );
  mem_1_5_97 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_5_FFX_RST,
      O => mem_1_5
    );
  mem_1_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_5_FFX_RST
    );
  mem_1_6_98 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_7_FFY_RST,
      O => mem_1_6
    );
  mem_1_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_7_FFY_RST
    );
  mem_2_0_99 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_1_FFY_RST,
      O => mem_2_0
    );
  mem_2_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_1_FFY_RST
    );
  mem_2_1_100 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_1_FFX_RST,
      O => mem_2_1
    );
  mem_2_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_1_FFX_RST
    );
  mem_1_7_101 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_7_FFX_RST,
      O => mem_1_7
    );
  mem_1_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_7_FFX_RST
    );
  mem_2_2_102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_3_FFY_RST,
      O => mem_2_2
    );
  mem_2_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_3_FFY_RST
    );
  mem_2_3_103 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_3_FFX_RST,
      O => mem_2_3
    );
  mem_2_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_3_FFX_RST
    );
  mem_2_4_104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_5_FFY_RST,
      O => mem_2_4
    );
  mem_2_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_5_FFY_RST
    );
  mem_2_5_105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_5_FFX_RST,
      O => mem_2_5
    );
  mem_2_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_5_FFX_RST
    );
  mem_2_6_106 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0005,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_2_7_FFY_RST,
      O => mem_2_6
    );
  mem_2_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_2_7_FFY_RST
    );
  mem_3_0_107 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0006,
      CLK => clk_BUFGP,
      SET => GND,
      RS