my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_3_OFF_RST,
      O => Mtridata_data_out(3)
    );
  data_out_3_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_3_OFF_RST
    );
  Mtrien_data_out_5_44 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_3_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_3_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_4
    );
  data_out_3_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_3_SRMUXNOT,
      O => data_out_3_TFF_SET
    );
  mem_0_6_45 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IDELAY,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_6_IFF_RST,
      O => mem_0_6
    );
  data_in_6_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_6_IFF_RST
    );
  mem_7_7_46 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IDELAY,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_7_IFF_RST,
      O => mem_7_7
    );
  data_in_7_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_7_IFF_RST
    );
  mem_0_0_47 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_0_1_FFY_RST,
      O => mem_0_0
    );
  mem_0_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_0_1_FFY_RST
    );
  mem_0_1_48 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_0_1_FFX_RST,
      O => mem_0_1
    );
  mem_0_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_0_1_FFX_RST
    );
  mem_0_2_49 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_0_3_FFY_RST,
      O => mem_0_2
    );
  mem_0_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_0_3_FFY_RST
    );
  mem_0_3_50 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_0_3_FFX_RST,
      O => mem_0_3
    );
  mem_0_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_0_3_FFX_RST
    );
  mem_1_2_51 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_3_FFY_RST,
      O => mem_1_2
    );
  mem_1_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_3_FFY_RST
    );
  mem_1_0_52 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_1_FFY_RST,
      O => mem_1_0
    );
  mem_1_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_1_FFY_RST
    );
  mem_1_1_53 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_1_FFX_RST,
      O => mem_1_1
    );
  mem_1_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_1_FFX_RST
    );
  mem_0_7_54 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0003,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_0_7_FFY_RST,
      O => mem_0_7
    );
  mem_0_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_0_7_FFY_RST
    );
  mem_1_3_55 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0004,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_1_3_FFX_RST,
      O => mem_1_3
    );
  mem_1_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_1_3_FFX_RST
    );
  mem_4_7_56 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_4_7_FFX_RST,
      O => mem_4_7
    );
  mem_4_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_4_7_FFX_RST
    );
  mem_5_2_57 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_3_FFY_RST,
      O => mem_5_2
    );
  mem_5_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_3_FFY_RST
    );
  mem_5_3_58 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_3_FFX_RST,
      O => mem_5_3
    );
  mem_5_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_3_FFX_RST
    );
  mem_5_4_59 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_5_FFY_RST,
      O => mem_5_4
    );
  mem_5_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_5_FFY_RST
    );
  mem_5_5_60 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_5_FFX_RST,
      O => mem_5_5
    );
  mem_5_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_5_FFX_RST
    );
  mem_5_6_61 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_7_FFY_RST,
      O => mem_5_6
    );
  mem_5_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_7_FFY_RST
    );
  mem_6_0_62 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_1_FFY_RST,
      O => mem_6_0
    );
  mem_6_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_1_FFY_RST
    );
  mem_6_1_63 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_1_FFX_RST,
      O => mem_6_1
    );
  mem_6_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_1_FFX_RST
    );
  mem_5_7_64 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0008,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_5_7_FFX_RST,
      O => mem_5_7
    );
  mem_5_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_5_7_FFX_RST
    );
  mem_6_2_65 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_3_FFY_RST,
      O => mem_6_2
    );
  mem_6_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_3_FFY_RST
    );
  mem_6_3_66 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_3_FFX_RST,
      O => mem_6_3
    );
  mem_6_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_3_FFX_RST
    );
  mem_6_4_67 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_5_FFY_RST,
      O => mem_6_4
    );
  mem_6_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_5_FFY_RST
    );
  mem_6_5_68 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_5_FFX_RST,
      O => mem_6_5
    );
  mem_6_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_5_FFX_RST
    );
  mem_6_6_69 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_7_FFY_RST,
      O => mem_6_6
    );
  mem_6_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_7_FFY_RST
    );
  mem_6_7_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF,
      CE => Q_n0009,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_6_7_FFX_RST,
      O => mem_6_7
    );
  mem_6_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_6_7_FFX_RST
    );
  mem_7_4_71 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,
      RST => mem_7_5_FFY_RST,
      O => mem_7_4
    );
  mem_7_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => mem_7_5_FFY_RST
    );
  Mtridata_data_out_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_4_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_4_OFF_RST,
      O => Mtridata_data_out(4)
    );
  data_out_4_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_4_OFF_RST
    );
  Mtrien_data_out_4_72 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_4_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_4_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_3
    );
  data_out_4_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_4_SRMUXNOT,
      O => data_out_4_TFF_SET
    );
  mem_7_0_73 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_0_IDELAY,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_in_0_IFF_RST,
      O => mem_7_0
    );
  data_in_0_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_in_0_IFF_RST
    );
  Mtridata_data_out_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_5_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_5_OFF_RST,
      O => Mtridata_data_out(5)
    );
  data_out_5_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_5_OFF_RST
    );
  Mtrien_data_out_3_74 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_5_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_5_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_2
    );
  data_out_5_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_5_SRMUXNOT,
      O => data_out_5_TFF_SET
    );
  mem_7_1_75 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_in_1_IDELAY,
      CE => Q_n0010,
      CLK => clk_BUFGP,
      SET => GND,