my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

  Mmux_n0002_net2_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net2_F5MUX,
      O => Mmux_n0002_net2
    );
  Mmux_n0002_inst_mux_f5_1 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_210_O,
      IB => Mmux_n0002_inst_lut3_32_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net5
    );
  Mmux_n0002_inst_lut3_32 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => mem_6_0,
      ADR1 => mem_7_0,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_32_O
    );
  Mmux_n0002_inst_lut3_210 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => mem_5_0,
      ADR1 => VCC,
      ADR2 => mem_4_0,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_210_O
    );
  Q_n0002_0_YUSED : X_BUF
    port map (
      I => Q_n0002_0_F6MUX,
      O => Q_n0002(0)
    );
  Mmux_n0002_inst_mux_f6_0 : X_MUX2
    port map (
      IA => Mmux_n0002_net2,
      IB => Mmux_n0002_net5,
      SEL => raddr_2_IBUF,
      O => Q_n0002_0_F6MUX
    );
  Mmux_n0002_inst_mux_f5_2 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_41_O,
      IB => Mmux_n0002_inst_lut3_51_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net9_F5MUX
    );
  Mmux_n0002_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_3_1,
      ADR3 => mem_2_1,
      O => Mmux_n0002_inst_lut3_51_O
    );
  Mmux_n0002_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => mem_1_1,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_0_1,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_41_O
    );
  Mmux_n0002_net9_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net9_F5MUX,
      O => Mmux_n0002_net9
    );
  Mmux_n0002_inst_mux_f5_3 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_61_O,
      IB => Mmux_n0002_inst_lut3_71_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net12
    );
  Mmux_n0002_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => mem_6_1,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => mem_7_1,
      O => Mmux_n0002_inst_lut3_71_O
    );
  Mmux_n0002_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => mem_5_1,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_4_1,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_61_O
    );
  Q_n0002_1_YUSED : X_BUF
    port map (
      I => Q_n0002_1_F6MUX,
      O => Q_n0002(1)
    );
  Mmux_n0002_inst_mux_f6_1 : X_MUX2
    port map (
      IA => Mmux_n0002_net9,
      IB => Mmux_n0002_net12,
      SEL => raddr_2_IBUF,
      O => Q_n0002_1_F6MUX
    );
  Mmux_n0002_inst_mux_f5_4 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_81_O,
      IB => Mmux_n0002_inst_lut3_91_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net16_F5MUX
    );
  Mmux_n0002_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => mem_3_2,
      ADR2 => mem_2_2,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_91_O
    );
  Mmux_n0002_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => mem_0_2,
      ADR1 => VCC,
      ADR2 => mem_1_2,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_81_O
    );
  Mmux_n0002_net16_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net16_F5MUX,
      O => Mmux_n0002_net16
    );
  Mmux_n0002_inst_mux_f5_5 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_101_O,
      IB => Mmux_n0002_inst_lut3_111_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net19
    );
  Mmux_n0002_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => mem_6_2,
      ADR1 => VCC,
      ADR2 => mem_7_2,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_111_O
    );
  Mmux_n0002_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => mem_4_2,
      ADR1 => VCC,
      ADR2 => mem_5_2,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_101_O
    );
  Q_n0002_2_YUSED : X_BUF
    port map (
      I => Q_n0002_2_F6MUX,
      O => Q_n0002(2)
    );
  Mmux_n0002_inst_mux_f6_2 : X_MUX2
    port map (
      IA => Mmux_n0002_net16,
      IB => Mmux_n0002_net19,
      SEL => raddr_2_IBUF,
      O => Q_n0002_2_F6MUX
    );
  Mmux_n0002_inst_mux_f5_6 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_121_O,
      IB => Mmux_n0002_inst_lut3_131_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net23_F5MUX
    );
  Mmux_n0002_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => mem_2_3,
      ADR1 => raddr_0_IBUF,
      ADR2 => VCC,
      ADR3 => mem_3_3,
      O => Mmux_n0002_inst_lut3_131_O
    );
  Mmux_n0002_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => mem_1_3,
      ADR1 => mem_0_3,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_121_O
    );
  Mmux_n0002_net23_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net23_F5MUX,
      O => Mmux_n0002_net23
    );
  Mmux_n0002_inst_mux_f5_7 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_141_O,
      IB => Mmux_n0002_inst_lut3_151_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net26
    );
  Mmux_n0002_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => mem_6_3,
      ADR2 => raddr_0_IBUF,
      ADR3 => mem_7_3,
      O => Mmux_n0002_inst_lut3_151_O
    );
  Mmux_n0002_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => mem_4_3,
      ADR1 => mem_5_3,
      ADR2 => raddr_0_IBUF,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_141_O
    );
  Q_n0002_3_YUSED : X_BUF
    port map (
      I => Q_n0002_3_F6MUX,
      O => Q_n0002(3)
    );
  Mmux_n0002_inst_mux_f6_3 : X_MUX2
    port map (
      IA => Mmux_n0002_net23,
      IB => Mmux_n0002_net26,
      SEL => raddr_2_IBUF,
      O => Q_n0002_3_F6MUX
    );
  Mmux_n0002_inst_mux_f5_8 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_161_O,
      IB => Mmux_n0002_inst_lut3_171_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net30_F5MUX
    );
  Mmux_n0002_inst_lut3_171 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => mem_2_4,
      ADR2 => VCC,
      ADR3 => mem_3_4,
      O => Mmux_n0002_inst_lut3_171_O
    );
  Mmux_n0002_inst_lut3_161 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => mem_0_4,
      ADR3 => mem_1_4,
      O => Mmux_n0002_inst_lut3_161_O
    );
  Mmux_n0002_net30_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net30_F5MUX,
      O => Mmux_n0002_net30
    );
  Mmux_n0002_inst_mux_f5_9 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_181_O,
      IB => Mmux_n0002_inst_lut3_191_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net33
    );
  Mmux_n0002_inst_lut3_191 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => mem_7_4,
      ADR1 => VCC,
      ADR2 => mem_6_4,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_191_O
    );
  Mmux_n0002_inst_lut3_181 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => mem_5_4,
      ADR2 => raddr_0_IBUF,
      ADR3 => mem_4_4,
      O => Mmux_n0002_inst_lut3_181_O
    );
  Q_n0002_4_YUSED : X_BUF
    port map (
      I => Q_n0002_4_F6MUX,
      O => Q_n0002(4)
    );
  Mmux_n0002_inst_mux_f6_4 : X_MUX2
    port map (
      IA => Mmux_n0002_net30,
      IB => Mmux_n0002_net33,
      SEL => raddr_2_IBUF,
      O => Q_n0002_4_F6MUX
    );
  Mtridata_data_out_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_1_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_1_OFF_RST,
      O => Mtridata_data_out(1)
    );
  data_out_1_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_1_OFF_RST
    );
  Mtrien_data_out_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_1_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_1_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_6
    );
  data_out_1_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_1_SRMUXNOT,
      O => data_out_1_TFF_SET
    );
  Ker10421 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => cs_IBUF,
      ADR2 => waddr_1_IBUF,
      ADR3 => we_IBUF,
      O => N1044_FROM
    );
  Q_n00081 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => waddr_2_IBUF,
      ADR3 => N1044,
      O => N1044_GROM
    );
  N1044_XUSED : X_BUF
    port map (
      I => N1044_FROM,
      O => N1044
    );
  N1044_YUSED : X_BUF
    port map (
      I => N1044_GROM,
      O => Q_n0008
    );
  Ker10351 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => we_IBUF,
      ADR1 => VCC,
      ADR2 => cs_IBUF,
      ADR3 => waddr_1_IBUF,
      O => N1037_FROM
    );
  Q_n00101 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => waddr_2_IBUF,
      ADR2 => waddr_0_IBUF,
      ADR3 => N1037,
      O => N1037_GROM
    );
  N1037_XUSED : X_BUF
    port map (
      I => N1037_FROM,
      O => N1037
    );
  N1037_YUSED : X_BUF
    port map (
      I => N1037_GROM,
      O => Q_n0010
    );
  Mtridata_data_out_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_2_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_2_OFF_RST,
      O => Mtridata_data_out(2)
    );
  data_out_2_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_2_OFF_RST
    );
  Q_n00041 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N1044,
      ADR2 => waddr_2_IBUF,
      ADR3 => waddr_0_IBUF,
      O => Q_n0004_FROM
    );
  Q_n00031 : X_LUT4
    generic map(
      INIT => X"000C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N1044,
      ADR2 => waddr_2_IBUF,
      ADR3 => waddr_0_IBUF,
      O => Q_n0004_GROM
    );
  Q_n0004_XUSED : X_BUF
    port map (
      I => Q_n0004_FROM,
      O => Q_n0004
    );
  Q_n0004_YUSED : X_BUF
    port map (
      I => Q_n0004_GROM,
      O => Q_n0003
    );
  Q_n00061 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => N1037,
      ADR1 => waddr_0_IBUF,
      ADR2 => waddr_2_IBUF,
      ADR3 => VCC,
      O => Q_n0006_FROM
    );
  Q_n00051 : X_LUT4
    generic map(
      INIT => X"0404"
    )
    port map (
      ADR0 => waddr_0_IBUF,
      ADR1 => N1037,
      ADR2 => waddr_2_IBUF,
      ADR3 => VCC,
      O => Q_n0006_GROM
    );
  Q_n0006_XUSED : X_BUF
    port map (
      I => Q_n0006_FROM,
      O => Q_n0006
    );
  Q_n0006_YUSED : X_BUF
    port map (
      I => Q_n0006_GROM,
      O => Q_n0005
    );
  Q_n00091 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => waddr_2_IBUF,
      ADR1 => VCC,
      ADR2 => N1037,
      ADR3 => waddr_0_IBUF,
      O => Q_n0009_FROM
    );
  Q_n00071 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N1044,
      ADR2 => waddr_0_IBUF,
      ADR3 => waddr_2_IBUF,
      O => Q_n0009_GROM
    );
  Q_n0009_XUSED : X_BUF
    port map (
      I => Q_n0009_FROM,
      O => Q_n0009
    );
  Q_n0009_YUSED : X_BUF
    port map (
      I => Q_n0009_GROM,
      O => Q_n0007
    );
  Mtrien_data_out_6_43 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_2_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_2_TFF_SET,
      RST => GND,
      O => Mtrien_data_out_5
    );
  data_out_2_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_2_SRMUXNOT,
      O => data_out_2_TFF_SET
    );
  Mtridata_data_out_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_3_OD,
      CE => VCC,