my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

      O => data_out(4)
    );
  data_out_4_ENABLEINV : X_INV
    port map (
      I => data_out_4_TORGTS,
      O => data_out_4_ENABLE
    );
  data_out_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_3,
      O => data_out_4_TORGTS
    );
  data_out_4_OUTMUX_27 : X_BUF
    port map (
      I => Mtridata_data_out(4),
      O => data_out_4_OUTMUX
    );
  data_out_4_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_4_TDATANOT
    );
  data_out_4_OMUX : X_BUF
    port map (
      I => Q_n0002(4),
      O => data_out_4_OD
    );
  data_out_4_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_4_SRMUXNOT
    );
  data_in_0_IMUX : X_BUF
    port map (
      I => data_in_0_IBUF_6,
      O => data_in_0_IBUF
    );
  data_in_0_IBUF_28 : X_BUF
    port map (
      I => data_in(0),
      O => data_in_0_IBUF_6
    );
  data_in_0_DELAY : X_BUF
    port map (
      I => data_in_0_IBUF_6,
      O => data_in_0_IDELAY
    );
  Mtridata_data_out_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_out_0_OD,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => data_out_0_OFF_RST,
      O => Mtridata_data_out(0)
    );
  data_out_0_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => data_out_0_OFF_RST
    );
  data_out_5_OBUFT : X_TRI
    port map (
      I => data_out_5_OUTMUX,
      CTL => data_out_5_ENABLE,
      O => data_out(5)
    );
  data_out_5_ENABLEINV : X_INV
    port map (
      I => data_out_5_TORGTS,
      O => data_out_5_ENABLE
    );
  data_out_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_2,
      O => data_out_5_TORGTS
    );
  data_out_5_OUTMUX_29 : X_BUF
    port map (
      I => Mtridata_data_out(5),
      O => data_out_5_OUTMUX
    );
  data_out_5_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_5_TDATANOT
    );
  data_out_5_OMUX : X_BUF
    port map (
      I => Q_n0002(5),
      O => data_out_5_OD
    );
  data_out_5_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_5_SRMUXNOT
    );
  data_in_1_IMUX : X_BUF
    port map (
      I => data_in_1_IBUF_7,
      O => data_in_1_IBUF
    );
  data_in_1_IBUF_30 : X_BUF
    port map (
      I => data_in(1),
      O => data_in_1_IBUF_7
    );
  data_in_1_DELAY : X_BUF
    port map (
      I => data_in_1_IBUF_7,
      O => data_in_1_IDELAY
    );
  data_out_6_OBUFT : X_TRI
    port map (
      I => data_out_6_OUTMUX,
      CTL => data_out_6_ENABLE,
      O => data_out(6)
    );
  data_out_6_ENABLEINV : X_INV
    port map (
      I => data_out_6_TORGTS,
      O => data_out_6_ENABLE
    );
  data_out_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_1,
      O => data_out_6_TORGTS
    );
  data_out_6_OUTMUX_31 : X_BUF
    port map (
      I => Mtridata_data_out(6),
      O => data_out_6_OUTMUX
    );
  data_out_6_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_6_TDATANOT
    );
  data_out_6_OMUX : X_BUF
    port map (
      I => Q_n0002(6),
      O => data_out_6_OD
    );
  data_out_6_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_6_SRMUXNOT
    );
  data_in_2_IMUX : X_BUF
    port map (
      I => data_in_2_IBUF_8,
      O => data_in_2_IBUF
    );
  data_in_2_IBUF_32 : X_BUF
    port map (
      I => data_in(2),
      O => data_in_2_IBUF_8
    );
  data_in_2_DELAY : X_BUF
    port map (
      I => data_in_2_IBUF_8,
      O => data_in_2_IDELAY
    );
  data_out_7_OBUFT : X_TRI
    port map (
      I => data_out_7_OUTMUX,
      CTL => data_out_7_ENABLE,
      O => data_out(7)
    );
  data_out_7_ENABLEINV : X_INV
    port map (
      I => data_out_7_TORGTS,
      O => data_out_7_ENABLE
    );
  data_out_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_0,
      O => data_out_7_TORGTS
    );
  data_out_7_OUTMUX_33 : X_BUF
    port map (
      I => Mtridata_data_out(7),
      O => data_out_7_OUTMUX
    );
  data_out_7_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_7_TDATANOT
    );
  data_out_7_OMUX : X_BUF
    port map (
      I => Q_n0002(7),
      O => data_out_7_OD
    );
  data_out_7_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_7_SRMUXNOT
    );
  data_in_3_IMUX : X_BUF
    port map (
      I => data_in_3_IBUF_9,
      O => data_in_3_IBUF
    );
  data_in_3_IBUF_34 : X_BUF
    port map (
      I => data_in(3),
      O => data_in_3_IBUF_9
    );
  data_in_3_DELAY : X_BUF
    port map (
      I => data_in_3_IBUF_9,
      O => data_in_3_IDELAY
    );
  data_in_4_IMUX : X_BUF
    port map (
      I => data_in_4_IBUF_10,
      O => data_in_4_IBUF
    );
  data_in_4_IBUF_35 : X_BUF
    port map (
      I => data_in(4),
      O => data_in_4_IBUF_10
    );
  data_in_4_DELAY : X_BUF
    port map (
      I => data_in_4_IBUF_10,
      O => data_in_4_IDELAY
    );
  data_in_5_IMUX : X_BUF
    port map (
      I => data_in_5_IBUF_11,
      O => data_in_5_IBUF
    );
  data_in_5_IBUF_36 : X_BUF
    port map (
      I => data_in(5),
      O => data_in_5_IBUF_11
    );
  data_in_5_DELAY : X_BUF
    port map (
      I => data_in_5_IBUF_11,
      O => data_in_5_IDELAY
    );
  data_in_6_IMUX : X_BUF
    port map (
      I => data_in_6_IBUF_12,
      O => data_in_6_IBUF
    );
  data_in_6_IBUF_37 : X_BUF
    port map (
      I => data_in(6),
      O => data_in_6_IBUF_12
    );
  data_in_6_DELAY : X_BUF
    port map (
      I => data_in_6_IBUF_12,
      O => data_in_6_IDELAY
    );
  waddr_0_IMUX : X_BUF
    port map (
      I => waddr_0_IBUF_13,
      O => waddr_0_IBUF
    );
  waddr_0_IBUF_38 : X_BUF
    port map (
      I => waddr(0),
      O => waddr_0_IBUF_13
    );
  data_in_7_IMUX : X_BUF
    port map (
      I => data_in_7_IBUF_14,
      O => data_in_7_IBUF
    );
  data_in_7_IBUF_39 : X_BUF
    port map (
      I => data_in(7),
      O => data_in_7_IBUF_14
    );
  data_in_7_DELAY : X_BUF
    port map (
      I => data_in_7_IBUF_14,
      O => data_in_7_IDELAY
    );
  waddr_1_IMUX : X_BUF
    port map (
      I => waddr_1_IBUF_15,
      O => waddr_1_IBUF
    );
  waddr_1_IBUF_40 : X_BUF
    port map (
      I => waddr(1),
      O => waddr_1_IBUF_15
    );
  Mtrien_data_out_41 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => data_out_0_TDATANOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => data_out_0_TFF_SET,
      RST => GND,
      O => Mtrien_data_out
    );
  data_out_0_TFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => data_out_0_SRMUXNOT,
      O => data_out_0_TFF_SET
    );
  waddr_2_IMUX : X_BUF
    port map (
      I => waddr_2_IBUF_16,
      O => waddr_2_IBUF
    );
  waddr_2_IBUF_42 : X_BUF
    port map (
      I => waddr(2),
      O => waddr_2_IBUF_16
    );
  Mmux_n0002_inst_mux_f5_10 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_201_O,
      IB => Mmux_n0002_inst_lut3_211_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net37_F5MUX
    );
  Mmux_n0002_inst_lut3_211 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => mem_2_5,
      ADR2 => mem_3_5,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_211_O
    );
  Mmux_n0002_inst_lut3_201 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => mem_1_5,
      ADR3 => mem_0_5,
      O => Mmux_n0002_inst_lut3_201_O
    );
  Mmux_n0002_net37_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net37_F5MUX,
      O => Mmux_n0002_net37
    );
  Mmux_n0002_inst_mux_f5_11 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_221_O,
      IB => Mmux_n0002_inst_lut3_231_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net40
    );
  Mmux_n0002_inst_lut3_231 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => mem_7_5,
      ADR1 => VCC,
      ADR2 => mem_6_5,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_231_O
    );
  Mmux_n0002_inst_lut3_221 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => mem_5_5,
      ADR1 => VCC,
      ADR2 => mem_4_5,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_221_O
    );
  Q_n0002_5_YUSED : X_BUF
    port map (
      I => Q_n0002_5_F6MUX,
      O => Q_n0002(5)
    );
  Mmux_n0002_inst_mux_f6_5 : X_MUX2
    port map (
      IA => Mmux_n0002_net37,
      IB => Mmux_n0002_net40,
      SEL => raddr_2_IBUF,
      O => Q_n0002_5_F6MUX
    );
  Mmux_n0002_inst_mux_f5_12 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_241_O,
      IB => Mmux_n0002_inst_lut3_251_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net44_F5MUX
    );
  Mmux_n0002_inst_lut3_251 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => mem_2_6,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => mem_3_6,
      O => Mmux_n0002_inst_lut3_251_O
    );
  Mmux_n0002_inst_lut3_241 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => mem_1_6,
      ADR1 => mem_0_6,
      ADR2 => raddr_0_IBUF,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_241_O
    );
  Mmux_n0002_net44_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net44_F5MUX,
      O => Mmux_n0002_net44
    );
  Mmux_n0002_inst_mux_f5_13 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_261_O,
      IB => Mmux_n0002_inst_lut3_271_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net47
    );
  Mmux_n0002_inst_lut3_271 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => mem_7_6,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_6_6,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_271_O
    );
  Mmux_n0002_inst_lut3_261 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => mem_5_6,
      ADR1 => raddr_0_IBUF,
      ADR2 => VCC,
      ADR3 => mem_4_6,
      O => Mmux_n0002_inst_lut3_261_O
    );
  Q_n0002_6_YUSED : X_BUF
    port map (
      I => Q_n0002_6_F6MUX,
      O => Q_n0002(6)
    );
  Mmux_n0002_inst_mux_f6_6 : X_MUX2
    port map (
      IA => Mmux_n0002_net44,
      IB => Mmux_n0002_net47,
      SEL => raddr_2_IBUF,
      O => Q_n0002_6_F6MUX
    );
  Mmux_n0002_inst_mux_f5_14 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_281_O,
      IB => Mmux_n0002_inst_lut3_291_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net51_F5MUX
    );
  Mmux_n0002_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => VCC,
      ADR2 => mem_2_7,
      ADR3 => mem_3_7,
      O => Mmux_n0002_inst_lut3_291_O
    );
  Mmux_n0002_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => mem_1_7,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_0_7,
      ADR3 => VCC,
      O => Mmux_n0002_inst_lut3_281_O
    );
  Mmux_n0002_net51_F5USED : X_BUF
    port map (
      I => Mmux_n0002_net51_F5MUX,
      O => Mmux_n0002_net51
    );
  Mmux_n0002_inst_mux_f5_15 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_301_O,
      IB => Mmux_n0002_inst_lut3_311_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net54
    );
  Mmux_n0002_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => mem_7_7,
      ADR1 => mem_6_7,
      ADR2 => VCC,
      ADR3 => raddr_0_IBUF,
      O => Mmux_n0002_inst_lut3_311_O
    );
  Mmux_n0002_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => raddr_0_IBUF,
      ADR2 => mem_4_7,
      ADR3 => mem_5_7,
      O => Mmux_n0002_inst_lut3_301_O
    );
  Q_n0002_7_YUSED : X_BUF
    port map (
      I => Q_n0002_7_F6MUX,
      O => Q_n0002(7)
    );
  Mmux_n0002_inst_mux_f6_7 : X_MUX2
    port map (
      IA => Mmux_n0002_net51,
      IB => Mmux_n0002_net54,
      SEL => raddr_2_IBUF,
      O => Q_n0002_7_F6MUX
    );
  Mmux_n0002_inst_mux_f5_0 : X_MUX2
    port map (
      IA => Mmux_n0002_inst_lut3_01_O,
      IB => Mmux_n0002_inst_lut3_110_O,
      SEL => raddr_1_IBUF,
      O => Mmux_n0002_net2_F5MUX
    );
  Mmux_n0002_inst_lut3_110 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => mem_3_0,
      ADR1 => VCC,
      ADR2 => raddr_0_IBUF,
      ADR3 => mem_2_0,
      O => Mmux_n0002_inst_lut3_110_O
    );
  Mmux_n0002_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => raddr_0_IBUF,
      ADR1 => mem_1_0,
      ADR2 => VCC,
      ADR3 => mem_0_0,
      O => Mmux_n0002_inst_lut3_01_O
    );