my_sram_timesim.vhd

FPGA系统的sram的软仿真设计

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 6 -pcf my_sram.pcf -ngm my_sram.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim my_sram.ncd my_sram_timesim.vhd 
-- Input file    : my_sram.ncd
-- Output file   : my_sram_timesim.vhd
-- Design name   : my_sram
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 2s15cs144-6 (PRODUCTION 1.27 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity my_sram is
  port (
    we : in STD_LOGIC := 'X'; 
    re : in STD_LOGIC := 'X'; 
    cs : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    data_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    waddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    raddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end my_sram;

architecture Structure of my_sram is
  signal cs_IBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal re_IBUF : STD_LOGIC; 
  signal we_IBUF : STD_LOGIC; 
  signal raddr_0_IBUF : STD_LOGIC; 
  signal raddr_1_IBUF : STD_LOGIC; 
  signal raddr_2_IBUF : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal Q_n0010 : STD_LOGIC; 
  signal mem_7_0 : STD_LOGIC; 
  signal data_in_0_IBUF : STD_LOGIC; 
  signal mem_7_1 : STD_LOGIC; 
  signal data_in_1_IBUF : STD_LOGIC; 
  signal mem_7_2 : STD_LOGIC; 
  signal data_in_2_IBUF : STD_LOGIC; 
  signal mem_7_3 : STD_LOGIC; 
  signal data_in_3_IBUF : STD_LOGIC; 
  signal Q_n0003 : STD_LOGIC; 
  signal mem_0_4 : STD_LOGIC; 
  signal data_in_4_IBUF : STD_LOGIC; 
  signal mem_0_5 : STD_LOGIC; 
  signal data_in_5_IBUF : STD_LOGIC; 
  signal mem_0_6 : STD_LOGIC; 
  signal data_in_6_IBUF : STD_LOGIC; 
  signal waddr_0_IBUF : STD_LOGIC; 
  signal mem_7_7 : STD_LOGIC; 
  signal data_in_7_IBUF : STD_LOGIC; 
  signal waddr_1_IBUF : STD_LOGIC; 
  signal waddr_2_IBUF : STD_LOGIC; 
  signal mem_2_5 : STD_LOGIC; 
  signal mem_3_5 : STD_LOGIC; 
  signal Mmux_n0002_net37 : STD_LOGIC; 
  signal mem_1_5 : STD_LOGIC; 
  signal mem_6_5 : STD_LOGIC; 
  signal mem_7_5 : STD_LOGIC; 
  signal mem_4_5 : STD_LOGIC; 
  signal mem_5_5 : STD_LOGIC; 
  signal mem_2_6 : STD_LOGIC; 
  signal mem_3_6 : STD_LOGIC; 
  signal Mmux_n0002_net44 : STD_LOGIC; 
  signal mem_1_6 : STD_LOGIC; 
  signal mem_6_6 : STD_LOGIC; 
  signal mem_7_6 : STD_LOGIC; 
  signal mem_4_6 : STD_LOGIC; 
  signal mem_5_6 : STD_LOGIC; 
  signal mem_2_7 : STD_LOGIC; 
  signal mem_3_7 : STD_LOGIC; 
  signal Mmux_n0002_net51 : STD_LOGIC; 
  signal mem_0_7 : STD_LOGIC; 
  signal mem_1_7 : STD_LOGIC; 
  signal mem_6_7 : STD_LOGIC; 
  signal mem_4_7 : STD_LOGIC; 
  signal mem_5_7 : STD_LOGIC; 
  signal mem_2_0 : STD_LOGIC; 
  signal mem_3_0 : STD_LOGIC; 
  signal Mmux_n0002_net2 : STD_LOGIC; 
  signal mem_0_0 : STD_LOGIC; 
  signal mem_1_0 : STD_LOGIC; 
  signal mem_6_0 : STD_LOGIC; 
  signal mem_4_0 : STD_LOGIC; 
  signal mem_5_0 : STD_LOGIC; 
  signal mem_2_1 : STD_LOGIC; 
  signal mem_3_1 : STD_LOGIC; 
  signal Mmux_n0002_net9 : STD_LOGIC; 
  signal mem_0_1 : STD_LOGIC; 
  signal mem_1_1 : STD_LOGIC; 
  signal mem_6_1 : STD_LOGIC; 
  signal mem_4_1 : STD_LOGIC; 
  signal mem_5_1 : STD_LOGIC; 
  signal mem_2_2 : STD_LOGIC; 
  signal mem_3_2 : STD_LOGIC; 
  signal Mmux_n0002_net16 : STD_LOGIC; 
  signal mem_0_2 : STD_LOGIC; 
  signal mem_1_2 : STD_LOGIC; 
  signal mem_6_2 : STD_LOGIC; 
  signal mem_4_2 : STD_LOGIC; 
  signal mem_5_2 : STD_LOGIC; 
  signal mem_2_3 : STD_LOGIC; 
  signal mem_3_3 : STD_LOGIC; 
  signal Mmux_n0002_net23 : STD_LOGIC; 
  signal mem_0_3 : STD_LOGIC; 
  signal mem_1_3 : STD_LOGIC; 
  signal mem_6_3 : STD_LOGIC; 
  signal mem_4_3 : STD_LOGIC; 
  signal mem_5_3 : STD_LOGIC; 
  signal mem_2_4 : STD_LOGIC; 
  signal mem_3_4 : STD_LOGIC; 
  signal Mmux_n0002_net30 : STD_LOGIC; 
  signal mem_1_4 : STD_LOGIC; 
  signal mem_6_4 : STD_LOGIC; 
  signal mem_7_4 : STD_LOGIC; 
  signal mem_4_4 : STD_LOGIC; 
  signal mem_5_4 : STD_LOGIC; 
  signal Q_n0004 : STD_LOGIC; 
  signal Q_n0005 : STD_LOGIC; 
  signal Q_n0006 : STD_LOGIC; 
  signal N1044 : STD_LOGIC; 
  signal Q_n0008 : STD_LOGIC; 
  signal Q_n0007 : STD_LOGIC; 
  signal N1037 : STD_LOGIC; 
  signal Q_n0009 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal cs_IBUF_0 : STD_LOGIC; 
  signal re_IBUF_1 : STD_LOGIC; 
  signal we_IBUF_2 : STD_LOGIC; 
  signal raddr_0_IBUF_3 : STD_LOGIC; 
  signal raddr_1_IBUF_4 : STD_LOGIC; 
  signal raddr_2_IBUF_5 : STD_LOGIC; 
  signal data_out_0_ENABLE : STD_LOGIC; 
  signal data_out_0_TORGTS : STD_LOGIC; 
  signal data_out_0_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out : STD_LOGIC; 
  signal data_out_0_TDATANOT : STD_LOGIC; 
  signal data_out_0_OD : STD_LOGIC; 
  signal data_out_0_SRMUXNOT : STD_LOGIC; 
  signal data_out_1_ENABLE : STD_LOGIC; 
  signal data_out_1_TORGTS : STD_LOGIC; 
  signal data_out_1_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_6 : STD_LOGIC; 
  signal data_out_1_TDATANOT : STD_LOGIC; 
  signal data_out_1_OD : STD_LOGIC; 
  signal data_out_1_SRMUXNOT : STD_LOGIC; 
  signal data_out_2_ENABLE : STD_LOGIC; 
  signal data_out_2_TORGTS : STD_LOGIC; 
  signal data_out_2_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_5 : STD_LOGIC; 
  signal data_out_2_TDATANOT : STD_LOGIC; 
  signal data_out_2_OD : STD_LOGIC; 
  signal data_out_2_SRMUXNOT : STD_LOGIC; 
  signal data_out_3_ENABLE : STD_LOGIC; 
  signal data_out_3_TORGTS : STD_LOGIC; 
  signal data_out_3_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_4 : STD_LOGIC; 
  signal data_out_3_TDATANOT : STD_LOGIC; 
  signal data_out_3_OD : STD_LOGIC; 
  signal data_out_3_SRMUXNOT : STD_LOGIC; 
  signal data_out_4_ENABLE : STD_LOGIC; 
  signal data_out_4_TORGTS : STD_LOGIC; 
  signal data_out_4_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_3 : STD_LOGIC; 
  signal data_out_4_TDATANOT : STD_LOGIC; 
  signal data_out_4_OD : STD_LOGIC; 
  signal data_out_4_SRMUXNOT : STD_LOGIC; 
  signal data_in_0_IDELAY : STD_LOGIC; 
  signal data_in_0_IBUF_6 : STD_LOGIC; 
  signal data_out_0_OFF_RST : STD_LOGIC; 
  signal data_out_5_ENABLE : STD_LOGIC; 
  signal data_out_5_TORGTS : STD_LOGIC; 
  signal data_out_5_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_2 : STD_LOGIC; 
  signal data_out_5_TDATANOT : STD_LOGIC; 
  signal data_out_5_OD : STD_LOGIC; 
  signal data_out_5_SRMUXNOT : STD_LOGIC; 
  signal data_in_1_IDELAY : STD_LOGIC; 
  signal data_in_1_IBUF_7 : STD_LOGIC; 
  signal data_out_6_ENABLE : STD_LOGIC; 
  signal data_out_6_TORGTS : STD_LOGIC; 
  signal data_out_6_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_1 : STD_LOGIC; 
  signal data_out_6_TDATANOT : STD_LOGIC; 
  signal data_out_6_OD : STD_LOGIC; 
  signal data_out_6_SRMUXNOT : STD_LOGIC; 
  signal data_in_2_IDELAY : STD_LOGIC; 
  signal data_in_2_IBUF_8 : STD_LOGIC; 
  signal data_out_7_ENABLE : STD_LOGIC; 
  signal data_out_7_TORGTS : STD_LOGIC; 
  signal data_out_7_OUTMUX : STD_LOGIC; 
  signal Mtrien_data_out_0 : STD_LOGIC; 
  signal data_out_7_TDATANOT : STD_LOGIC; 
  signal data_out_7_OD : STD_LOGIC; 
  signal data_out_7_SRMUXNOT : STD_LOGIC; 
  signal data_in_3_IDELAY : STD_LOGIC; 
  signal data_in_3_IBUF_9 : STD_LOGIC; 
  signal data_in_4_IDELAY : STD_LOGIC; 
  signal data_in_4_IBUF_10 : STD_LOGIC; 
  signal data_in_5_IDELAY : STD_LOGIC; 
  signal data_in_5_IBUF_11 : STD_LOGIC; 
  signal data_in_6_IDELAY : STD_LOGIC; 
  signal data_in_6_IBUF_12 : STD_LOGIC; 
  signal waddr_0_IBUF_13 : STD_LOGIC; 
  signal data_in_7_IDELAY : STD_LOGIC; 
  signal data_in_7_IBUF_14 : STD_LOGIC; 
  signal waddr_1_IBUF_15 : STD_LOGIC; 
  signal data_out_0_TFF_SET : STD_LOGIC; 
  signal waddr_2_IBUF_16 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_211_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_201_O : STD_LOGIC; 
  signal Mmux_n0002_net37_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_231_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_221_O : STD_LOGIC; 
  signal Q_n0002_5_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net40 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_251_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_241_O : STD_LOGIC; 
  signal Mmux_n0002_net44_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_271_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_261_O : STD_LOGIC; 
  signal Q_n0002_6_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net47 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_291_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_281_O : STD_LOGIC; 
  signal Mmux_n0002_net51_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_311_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_301_O : STD_LOGIC; 
  signal Q_n0002_7_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net54 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_110_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_01_O : STD_LOGIC; 
  signal Mmux_n0002_net2_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_32_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_210_O : STD_LOGIC; 
  signal Q_n0002_0_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net5 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_51_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_41_O : STD_LOGIC; 
  signal Mmux_n0002_net9_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_71_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_61_O : STD_LOGIC; 
  signal Q_n0002_1_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net12 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_91_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_81_O : STD_LOGIC; 
  signal Mmux_n0002_net16_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_111_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_101_O : STD_LOGIC; 
  signal Q_n0002_2_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net19 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_131_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_121_O : STD_LOGIC; 
  signal Mmux_n0002_net23_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_151_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_141_O : STD_LOGIC; 
  signal Q_n0002_3_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net26 : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_171_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_161_O : STD_LOGIC; 
  signal Mmux_n0002_net30_F5MUX : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_191_O : STD_LOGIC; 
  signal Mmux_n0002_inst_lut3_181_O : STD_LOGIC; 
  signal Q_n0002_4_F6MUX : STD_LOGIC; 
  signal Mmux_n0002_net33 : STD_LOGIC; 
  signal data_out_1_OFF_RST : STD_LOGIC; 
  signal data_out_1_TFF_SET : STD_LOGIC; 
  signal N1044_FROM : STD_LOGIC; 
  signal N1044_GROM : STD_LOGIC; 
  signal N1037_FROM : STD_LOGIC; 
  signal N1037_GROM : STD_LOGIC; 
  signal data_out_2_OFF_RST : STD_LOGIC; 
  signal Q_n0004_FROM : STD_LOGIC; 
  signal Q_n0004_GROM : STD_LOGIC; 
  signal Q_n0006_FROM : STD_LOGIC; 
  signal Q_n0006_GROM : STD_LOGIC; 
  signal Q_n0009_FROM : STD_LOGIC; 
  signal Q_n0009_GROM : STD_LOGIC; 
  signal data_out_2_TFF_SET : STD_LOGIC; 
  signal data_out_3_OFF_RST : STD_LOGIC; 
  signal data_out_3_TFF_SET : STD_LOGIC; 
  signal data_in_6_IFF_RST : STD_LOGIC; 
  signal data_in_7_IFF_RST : STD_LOGIC; 
  signal mem_0_1_FFY_RST : STD_LOGIC; 
  signal mem_0_1_FFX_RST : STD_LOGIC; 
  signal mem_0_3_FFY_RST : STD_LOGIC; 
  signal mem_0_3_FFX_RST : STD_LOGIC; 
  signal mem_1_3_FFY_RST : STD_LOGIC; 
  signal mem_1_1_FFY_RST : STD_LOGIC; 
  signal mem_1_1_FFX_RST : STD_LOGIC; 
  signal mem_0_7_FFY_RST : STD_LOGIC; 
  signal mem_1_3_FFX_RST : STD_LOGIC; 
  signal mem_4_7_FFX_RST : STD_LOGIC; 
  signal mem_5_3_FFY_RST : STD_LOGIC; 
  signal mem_5_3_FFX_RST : STD_LOGIC; 
  signal mem_5_5_FFY_RST : STD_LOGIC; 
  signal mem_5_5_FFX_RST : STD_LOGIC; 
  signal mem_5_7_FFY_RST : STD_LOGIC; 
  signal mem_6_1_FFY_RST : STD_LOGIC; 
  signal mem_6_1_FFX_RST : STD_LOGIC; 
  signal mem_5_7_FFX_RST : STD_LOGIC; 
  signal mem_6_3_FFY_RST : STD_LOGIC; 
  signal mem_6_3_FFX_RST : STD_LOGIC; 
  signal mem_6_5_FFY_RST : STD_LOGIC; 
  signal mem_6_5_FFX_RST : STD_LOGIC; 
  signal mem_6_7_FFY_RST : STD_LOGIC; 
  signal mem_6_7_FFX_RST : STD_LOGIC; 
  signal mem_7_5_FFY_RST : STD_LOGIC; 
  signal data_out_4_OFF_RST : STD_LOGIC; 
  signal data_out_4_TFF_SET : STD_LOGIC; 
  signal data_in_0_IFF_RST : STD_LOGIC; 
  signal data_out_5_OFF_RST : STD_LOGIC; 
  signal data_out_5_TFF_SET : STD_LOGIC; 
  signal data_in_1_IFF_RST : STD_LOGIC; 
  signal data_out_6_OFF_RST : STD_LOGIC; 
  signal mem_3_3_FFX_RST : STD_LOGIC; 
  signal mem_3_5_FFY_RST : STD_LOGIC; 
  signal mem_3_5_FFX_RST : STD_LOGIC; 
  signal mem_4_1_FFY_RST : STD_LOGIC; 
  signal mem_4_1_FFX_RST : STD_LOGIC; 
  signal mem_3_7_FFY_RST : STD_LOGIC; 
  signal mem_3_7_FFX_RST : STD_LOGIC; 
  signal mem_4_3_FFY_RST : STD_LOGIC; 
  signal mem_4_3_FFX_RST : STD_LOGIC; 
  signal mem_4_5_FFY_RST : STD_LOGIC; 
  signal mem_4_5_FFX_RST : STD_LOGIC; 
  signal mem_4_7_FFY_RST : STD_LOGIC; 
  signal mem_5_1_FFY_RST : STD_LOGIC; 
  signal mem_5_1_FFX_RST : STD_LOGIC; 
  signal data_out_6_TFF_SET : STD_LOGIC; 
  signal data_in_2_IFF_RST : STD_LOGIC; 
  signal data_out_7_OFF_RST : STD_LOGIC; 
  signal data_out_7_TFF_SET : STD_LOGIC; 
  signal data_in_3_IFF_RST : STD_LOGIC; 
  signal data_in_4_IFF_RST : STD_LOGIC; 
  signal data_in_5_IFF_RST : STD_LOGIC; 
  signal mem_1_5_FFY_RST : STD_LOGIC; 
  signal mem_1_5_FFX_RST : STD_LOGIC; 
  signal mem_1_7_FFY_RST : STD_LOGIC; 
  signal mem_2_1_FFY_RST : STD_LOGIC; 
  signal mem_2_1_FFX_RST : STD_LOGIC; 
  signal mem_1_7_FFX_RST : STD_LOGIC; 
  signal mem_2_3_FFY_RST : STD_LOGIC; 
  signal mem_2_3_FFX_RST : STD_LOGIC; 
  signal mem_2_5_FFY_RST : STD_LOGIC; 
  signal mem_2_5_FFX_RST : STD_LOGIC; 
  signal mem_2_7_FFY_RST : STD_LOGIC; 
  signal mem_3_1_FFY_RST : STD_LOGIC; 
  signal mem_3_1_FFX_RST : STD_LOGIC; 
  signal mem_2_7_FFX_RST : STD_LOGIC; 
  signal mem_3_3_FFY_RST : STD_LOGIC; 
  signal mem_7_5_FFX_RST : STD_LOGIC; 
  signal mem_7_6_FFY_RST : STD_LOGIC; 
  signal clk_BUFGP_BUFG_CE : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Q_n0002 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mtridata_data_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  cs_IMUX : X_BUF
    port map (
      I => cs_IBUF_0,
      O => cs_IBUF
    );
  cs_IBUF_17 : X_BUF
    port map (
      I => cs,
      O => cs_IBUF_0
    );
  re_IMUX : X_BUF
    port map (
      I => re_IBUF_1,
      O => re_IBUF
    );
  re_IBUF_18 : X_BUF
    port map (
      I => re,
      O => re_IBUF_1
    );
  we_IMUX : X_BUF
    port map (
      I => we_IBUF_2,
      O => we_IBUF
    );
  we_IBUF_19 : X_BUF
    port map (
      I => we,
      O => we_IBUF_2
    );
  raddr_0_IMUX : X_BUF
    port map (
      I => raddr_0_IBUF_3,
      O => raddr_0_IBUF
    );
  raddr_0_IBUF_20 : X_BUF
    port map (
      I => raddr(0),
      O => raddr_0_IBUF_3
    );
  raddr_1_IMUX : X_BUF
    port map (
      I => raddr_1_IBUF_4,
      O => raddr_1_IBUF
    );
  raddr_1_IBUF_21 : X_BUF
    port map (
      I => raddr(1),
      O => raddr_1_IBUF_4
    );
  raddr_2_IMUX : X_BUF
    port map (
      I => raddr_2_IBUF_5,
      O => raddr_2_IBUF
    );
  raddr_2_IBUF_22 : X_BUF
    port map (
      I => raddr(2),
      O => raddr_2_IBUF_5
    );
  data_out_0_OBUFT : X_TRI
    port map (
      I => data_out_0_OUTMUX,
      CTL => data_out_0_ENABLE,
      O => data_out(0)
    );
  data_out_0_ENABLEINV : X_INV
    port map (
      I => data_out_0_TORGTS,
      O => data_out_0_ENABLE
    );
  data_out_0_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out,
      O => data_out_0_TORGTS
    );
  data_out_0_OUTMUX_23 : X_BUF
    port map (
      I => Mtridata_data_out(0),
      O => data_out_0_OUTMUX
    );
  data_out_0_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_0_TDATANOT
    );
  data_out_0_OMUX : X_BUF
    port map (
      I => Q_n0002(0),
      O => data_out_0_OD
    );
  data_out_0_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_0_SRMUXNOT
    );
  data_out_1_OBUFT : X_TRI
    port map (
      I => data_out_1_OUTMUX,
      CTL => data_out_1_ENABLE,
      O => data_out(1)
    );
  data_out_1_ENABLEINV : X_INV
    port map (
      I => data_out_1_TORGTS,
      O => data_out_1_ENABLE
    );
  data_out_1_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_6,
      O => data_out_1_TORGTS
    );
  data_out_1_OUTMUX_24 : X_BUF
    port map (
      I => Mtridata_data_out(1),
      O => data_out_1_OUTMUX
    );
  data_out_1_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_1_TDATANOT
    );
  data_out_1_OMUX : X_BUF
    port map (
      I => Q_n0002(1),
      O => data_out_1_OD
    );
  data_out_1_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_1_SRMUXNOT
    );
  data_out_2_OBUFT : X_TRI
    port map (
      I => data_out_2_OUTMUX,
      CTL => data_out_2_ENABLE,
      O => data_out(2)
    );
  data_out_2_ENABLEINV : X_INV
    port map (
      I => data_out_2_TORGTS,
      O => data_out_2_ENABLE
    );
  data_out_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_5,
      O => data_out_2_TORGTS
    );
  data_out_2_OUTMUX_25 : X_BUF
    port map (
      I => Mtridata_data_out(2),
      O => data_out_2_OUTMUX
    );
  data_out_2_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_2_TDATANOT
    );
  data_out_2_OMUX : X_BUF
    port map (
      I => Q_n0002(2),
      O => data_out_2_OD
    );
  data_out_2_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_2_SRMUXNOT
    );
  data_out_3_OBUFT : X_TRI
    port map (
      I => data_out_3_OUTMUX,
      CTL => data_out_3_ENABLE,
      O => data_out(3)
    );
  data_out_3_ENABLEINV : X_INV
    port map (
      I => data_out_3_TORGTS,
      O => data_out_3_ENABLE
    );
  data_out_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => Mtrien_data_out_4,
      O => data_out_3_TORGTS
    );
  data_out_3_OUTMUX_26 : X_BUF
    port map (
      I => Mtridata_data_out(3),
      O => data_out_3_OUTMUX
    );
  data_out_3_TRIMUX : X_INV
    port map (
      I => re_IBUF,
      O => data_out_3_TDATANOT
    );
  data_out_3_OMUX : X_BUF
    port map (
      I => Q_n0002(3),
      O => data_out_3_OD
    );
  data_out_3_SRMUX : X_INV
    port map (
      I => cs_IBUF,
      O => data_out_3_SRMUXNOT
    );
  data_out_4_OBUFT : X_TRI
    port map (
      I => data_out_4_OUTMUX,
      CTL => data_out_4_ENABLE,