my_sram_timesim.nlf

FPGA系统的sram的软仿真设计

Release 6.3i - netgen G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "my_sram.ncd".
   "my_sram" is an NCD, version 2.38, device xc2s15, package cs144, speed -6
Loading device for application netgen from file '2s15.nph' in environment
D:/Xilinx.
Loading constraints from file "my_sram.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist my_sram_timesim.vhd ...
Writing VHDL SDF file my_sram_timesim.sdf ...
Total memory usage is 46348 kilobytes