cpu86.vhd

Run Pac-man Game Based on 8086/8088 FPGA IP Core

   signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle

   TYPE STATE_TYPE IS (
      Sreset,
      Sws,
      Smaxws,
      Sack,
      Srdopc,
      Serror,
      Swrite,
      Swsw,
      Smaxwsw,
      Sackw,
      Swrodd,
      Sread,
      Srdodd1,
      Swsr,
      Smaxwsr,
      Sackr,
      Sflush1,
      Sfull,
      Sint,
      Sintws,
      Sflush2
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";

   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE;
   SIGNAL next_state		: STATE_TYPE;

   -- Declare any pre-registered internal signals
   SIGNAL biu_error_cld : std_logic ;

BEGIN

   -----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk,
      reset
   )
   -----------------------------------------------------------------
   BEGIN
      IF (reset = '1') THEN
         current_state <= Sreset;
         -- Default Reset Values
         biu_error_cld <= '0';
         oddflag_s <= '0';
         ws_s <= (others=>'0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
         -- Default Assignment To Internals
         ws_s <= (others=>'0');
         biu_error_cld <= '0';

         -- Combined Actions
         CASE current_state IS
            WHEN Sws => 
               ws_s <= ws_s + '1';
            WHEN Sack => 
               oddflag_s<='0';
            WHEN Srdopc => 
               ws_s <= (others=>'0');
            WHEN Serror => 
               biu_error_cld <= '1';
            WHEN Swrite => 
               ws_s <= (others=>'0');
               oddflag_s<='0';
            WHEN Swsw => 
               ws_s <= ws_s + '1';
            WHEN Swrodd => 
               ws_s <= (others=>'0');
               oddflag_s<='1';
            WHEN Sread => 
               ws_s <= (others=>'0');
               oddflag_s<='0';
            WHEN Srdodd1 => 
               ws_s <= (others=>'0');
               oddflag_s<='1';
            WHEN Swsr => 
               ws_s <= ws_s + '1';
            WHEN OTHERS =>
               NULL;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      flush_coming,
      flush_req,
      irq,
      irq_type,
      opc_req,
      read_req,
      reg1freed,
      reg4free,
      regnbok,
      rwmem3_s,
      write_req,
      ws_s
   )
   -----------------------------------------------------------------
   BEGIN
      -- Default Assignment
      addrplus4 <= '0';
      irq_clr <= '0';
      latchabus <= '0';
      latchclr <= '0';
      latchm <= '0';
      latcho <= '0';
      latchrw <= '0';
      ldposplus1 <= '0';
      muxabus <= "00";
      rdcode_s <= '0';
      rddata_s <= '0';
      regplus1 <= '0';
      rw_ack <= '0';
      wr_s <= '0';
      flush_ack <= '0';
      inta1 <= '0';

      -- Combined Actions
      CASE current_state IS
         WHEN Sreset => 
            latchrw <= '1' ;
            next_state <= Srdopc;
         WHEN Sws => 
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxws;
            ELSE
               next_state <= Sws;
            END IF;
         WHEN Smaxws => 
            latchabus<='1';
            addrplus4<='1'; 
            latchclr <= '1' ;
            ldposplus1<='1';
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSE
               next_state <= Sack;
            END IF;
         WHEN Sack => 
            latchm<=reg1freed; 
            regplus1<='1';
            IF (write_req = '1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Swrite;
            ELSIF (read_req = '1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Sread;
            ELSIF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (irq='1' AND opc_req='1') THEN 
               next_state <= Sint;
            ELSIF (reg4free = '1' AND
                   flush_coming='0' AND
                   irq='0') THEN 
               latchrw <= '1' ;
               next_state <= Srdopc;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               next_state <= Sfull;
            END IF;
         WHEN Srdopc => 
            rdcode_s <= '1';
            latcho <= regnbok and opc_req;
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (ws_s/=MAX_WS) THEN 
               next_state <= Sws;
            ELSE
               next_state <= Smaxws;
            END IF;
         WHEN Serror => 
            next_state <= Serror;
         WHEN Swrite => 
            wr_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsw;
            ELSE
               next_state <= Smaxwsw;
            END IF;
         WHEN Swsw => 
            latcho <= regnbok and opc_req;
            IF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxwsw;
            ELSE
               next_state <= Swsw;
            END IF;
         WHEN Smaxwsw => 
            latcho <= regnbok and opc_req;
            latchclr <= '1' ;
            rw_ack<= not rwmem3_s;
            next_state <= Sackw;
         WHEN Sackw => 
            latcho <= regnbok and opc_req;
            IF (rwmem3_s = '1') THEN 
               muxabus <="10";
               latchrw<='1';
               next_state <= Swrodd;
            ELSIF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (flush_coming='1' OR
                   (irq='1' AND opc_req='0')) THEN 
               next_state <= Sfull;
            ELSIF (irq='1' AND opc_req='1') THEN 
               next_state <= Sint;
            ELSIF (reg4free = '1' ) THEN 
               muxabus <="00";
               latchrw<='1';
               next_state <= Srdopc;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               muxabus <="00";
               next_state <= Sack;
            END IF;
         WHEN Swrodd => 
            latcho <= regnbok and opc_req;
            wr_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsw;
            ELSE
               next_state <= Smaxwsw;
            END IF;
         WHEN Sread => 
            rddata_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsr;
            ELSE
               next_state <= Smaxwsr;
            END IF;
         WHEN Srdodd1 => 
            rddata_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsr;
            ELSE
               next_state <= Smaxwsr;
            END IF;
         WHEN Swsr => 
            IF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxwsr;
            ELSE
               next_state <= Swsr;
            END IF;
         WHEN Smaxwsr => 
            latchclr <= '1' ;
            rw_ack<= not rwmem3_s;
            next_state <= Sackr;
         WHEN Sackr => 
            IF (rwmem3_s = '1') THEN 
               muxabus <="10";
               latchrw <= '1';
               next_state <= Srdodd1;
            ELSIF (flush_coming='1' OR
                   (irq='1' AND opc_req='0')) THEN 
               next_state <= Sfull;
            ELSIF (irq='1' AND opc_req='1') THEN 
               next_state <= Sint;
            ELSIF (reg4free = '1' ) THEN 
               muxabus <="00";
               latchrw<='1';
               next_state <= Srdopc;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN