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-- CONST & instr.irg(3 downto 0)
constant ALU_SAHF : std_logic_vector(6 downto 0) := "0001110"; -- AH -> Flags
-- CONST & instr.irg(3 downto 0)
constant ALU_LAHF : std_logic_vector(6 downto 0) := "0001111"; -- Flags->ALUBUS (->AH)
-- CONSTANT & instr.ireg(1) & modrm.reg(5 downto 3)
-- CONSTANT=001
constant ALU_ROL1 : std_logic_vector(6 downto 0) := "0010000"; -- count=1
constant ALU_ROR1 : std_logic_vector(6 downto 0) := "0010001";
constant ALU_RCL1 : std_logic_vector(6 downto 0) := "0010010";
constant ALU_RCR1 : std_logic_vector(6 downto 0) := "0010011";
constant ALU_SHL1 : std_logic_vector(6 downto 0) := "0010100";
constant ALU_SHR1 : std_logic_vector(6 downto 0) := "0010101";
constant ALU_SAR1 : std_logic_vector(6 downto 0) := "0010111";
constant ALU_ROL : std_logic_vector(6 downto 0) := "0011000"; -- Count in CL
constant ALU_ROR : std_logic_vector(6 downto 0) := "0011001";
constant ALU_RCL : std_logic_vector(6 downto 0) := "0011010";
constant ALU_RCR : std_logic_vector(6 downto 0) := "0011011";
constant ALU_SHL : std_logic_vector(6 downto 0) := "0011100";
constant ALU_SHR : std_logic_vector(6 downto 0) := "0011101";
constant ALU_SAR : std_logic_vector(6 downto 0) := "0011111";
-- CONST & modrm.reg(5 downto 3)/instr.ireg(5 downto 3)
constant ALU_INC : std_logic_vector(6 downto 0) := "0100000"; -- Increment
constant ALU_DEC : std_logic_vector(6 downto 0) := "0100001"; -- Decrement also used for LOOP/JCXZ
-- Note ALU_DEC is also used as a constant for LOOP/JCXZ instr, perhaps add these to ALU operations?
constant ALU_CLRTIF : std_logic_vector(6 downto 0) := "0100010"; -- Clear TF/IF flag, used for INT
constant ALU_CMPS : std_logic_vector(6 downto 0) := "0100111"; -- Compare String ALUREG-MDBUS
constant ALU_SCAS : std_logic_vector(6 downto 0) := "0101111"; -- AX/AL-MDBUS, no SEXT
-- CONST & instr.irg(3 downto 0)
constant ALU_CMC : std_logic_vector(6 downto 0) := "0100101"; -- Complement Carry
constant ALU_CLC : std_logic_vector(6 downto 0) := "0101000"; -- Clear Carry
constant ALU_STC : std_logic_vector(6 downto 0) := "0101001"; -- Set Carry
constant ALU_CLI : std_logic_vector(6 downto 0) := "0101010"; -- Clear interrupt
constant ALU_STI : std_logic_vector(6 downto 0) := "0101011"; -- Set Interrupt
constant ALU_CLD : std_logic_vector(6 downto 0) := "0101100"; -- Clear Direction
constant ALU_STD : std_logic_vector(6 downto 0) := "0101101"; -- Set Direction
-- CONST & modrm.reg(5 downto 3)
-- Note bit3 is added/changed by proc and not connected to ireg(3)
constant ALU_TEST2: std_logic_vector(6 downto 0) := "0110000"; -- F6/F7
constant ALU_NOT : std_logic_vector(6 downto 0) := "0110010"; -- F6/F7
constant ALU_NEG : std_logic_vector(6 downto 0) := "0110011"; -- F6/F7
constant ALU_MUL : std_logic_vector(6 downto 0) := "0110100"; -- F6/F7
constant ALU_IMUL : std_logic_vector(6 downto 0) := "0110101"; -- F6/F7
constant ALU_DIV : std_logic_vector(6 downto 0) := "0110110"; -- F6/F7
constant ALU_IDIV : std_logic_vector(6 downto 0) := "0110111"; -- F6/F7
-- Second cycle write DX
constant ALU_MUL2 : std_logic_vector(6 downto 0) := "0111100"; -- F6/F7
constant ALU_IMUL2 : std_logic_vector(6 downto 0) := "0111101"; -- F6/F7
constant ALU_DIV2 : std_logic_vector(6 downto 0) := "0111110"; -- F6/F7
constant ALU_IDIV2 : std_logic_vector(6 downto 0) := "0111111"; -- F6/F7
-- CONST & instr.ireg(3 downto 0)
constant ALU_SEXT : std_logic_vector(6 downto 0) := "0111000"; -- Used for CBW
constant ALU_SEXTW : std_logic_vector(6 downto 0) := "0111001"; -- Used for CWD
-- CONSTANT & & instr.ireg(1) & instr.ireg(5 downto 3)
constant ALU_AAM : std_logic_vector(6 downto 0) := "1000010";
constant ALU_AAD : std_logic_vector(6 downto 0) := "1001010";
constant ALU_DAA : std_logic_vector(6 downto 0) := "1001100";
constant ALU_DAS : std_logic_vector(6 downto 0) := "1001101";
constant ALU_AAA : std_logic_vector(6 downto 0) := "1001110";
constant ALU_AAS : std_logic_vector(6 downto 0) := "1001111";
---------------------------------------------------------------
-- ALU Operations using sign extended data (SW=11)
-- ireg(1) & ireg(1) & '0' reg(5 downto 3) S+S+0+reg(5..3)
-- CONSTANT=110
constant ALU_ADD_SE : std_logic_vector(6 downto 0) := "1100000";
constant ALU_OR_SE : std_logic_vector(6 downto 0) := "1100001";
constant ALU_ADC_SE : std_logic_vector(6 downto 0) := "1100010";
constant ALU_SBB_SE : std_logic_vector(6 downto 0) := "1100011";
constant ALU_AND_SE : std_logic_vector(6 downto 0) := "1100100";
constant ALU_SUB_SE : std_logic_vector(6 downto 0) := "1100101";
constant ALU_XOR_SE : std_logic_vector(6 downto 0) := "1100110";
constant ALU_CMP_SE : std_logic_vector(6 downto 0) := "1100111";
END cpu86pack;
--
-- VHDL Package Header cpu.instr
--
-- Created:
-- by - Administrator.UNKNOWN (ACHILLES)
-- at - 19:42:25 21/01/2002
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5b (Build 9)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE cpu86instr IS
-----------------------------------------------------------------------------
-- INC/DEC Word Register
-----------------------------------------------------------------------------
constant INCREG0 : std_logic_vector(7 downto 0) := X"40"; -- Inc Register
constant INCREG1 : std_logic_vector(7 downto 0) := X"41";
constant INCREG2 : std_logic_vector(7 downto 0) := X"42";
constant INCREG3 : std_logic_vector(7 downto 0) := X"43";
constant INCREG4 : std_logic_vector(7 downto 0) := X"44";
constant INCREG5 : std_logic_vector(7 downto 0) := X"45";
constant INCREG6 : std_logic_vector(7 downto 0) := X"46";
constant INCREG7 : std_logic_vector(7 downto 0) := X"47";
constant DECREG0 : std_logic_vector(7 downto 0) := X"48"; -- DEC Register
constant DECREG1 : std_logic_vector(7 downto 0) := X"49";
constant DECREG2 : std_logic_vector(7 downto 0) := X"4A";
constant DECREG3 : std_logic_vector(7 downto 0) := X"4B";
constant DECREG4 : std_logic_vector(7 downto 0) := X"4C";
constant DECREG5 : std_logic_vector(7 downto 0) := X"4D";
constant DECREG6 : std_logic_vector(7 downto 0) := X"4E";
constant DECREG7 : std_logic_vector(7 downto 0) := X"4F";
-----------------------------------------------------------------------------
-- IN
-----------------------------------------------------------------------------
constant INFIXED0 : std_logic_vector(7 downto 0) := X"E4"; -- Fixed Port Byte
constant INFIXED1 : std_logic_vector(7 downto 0) := X"E5"; -- Fixed Port Word
constant INDX0 : std_logic_vector(7 downto 0) := X"EC"; -- DX Byte
constant INDX1 : std_logic_vector(7 downto 0) := X"ED"; -- DX Word
-----------------------------------------------------------------------------
-- OUT
-----------------------------------------------------------------------------
constant OUTFIXED0 : std_logic_vector(7 downto 0) := X"E6"; -- Fixed Port Byte
constant OUTFIXED1 : std_logic_vector(7 downto 0) := X"E7"; -- Fixed Port Word
constant OUTDX0 : std_logic_vector(7 downto 0) := X"EE"; -- DX Byte
constant OUTDX1 : std_logic_vector(7 downto 0) := X"EF"; -- DX Word
-----------------------------------------------------------------------------
-- Move Immediate to Register
-----------------------------------------------------------------------------
constant MOVI2R0 : std_logic_vector(7 downto 0) := X"B0"; -- Immediate to Register
constant MOVI2R1 : std_logic_vector(7 downto 0) := X"B1"; -- Byte
constant MOVI2R2 : std_logic_vector(7 downto 0) := X"B2";
constant MOVI2R3 : std_logic_vector(7 downto 0) := X"B3";
constant MOVI2R4 : std_logic_vector(7 downto 0) := X"B4";
constant MOVI2R5 : std_logic_vector(7 downto 0) := X"B5";
constant MOVI2R6 : std_logic_vector(7 downto 0) := X"B6";
constant MOVI2R7 : std_logic_vector(7 downto 0) := X"B7";
constant MOVI2R8 : std_logic_vector(7 downto 0) := X"B8"; -- Word
constant MOVI2R9 : std_logic_vector(7 downto 0) := X"B9";
constant MOVI2R10 : std_logic_vector(7 downto 0) := X"BA";
constant MOVI2R11 : std_logic_vector(7 downto 0) := X"BB";
constant MOVI2R12 : std_logic_vector(7 downto 0) := X"BC";
constant MOVI2R13 : std_logic_vector(7 downto 0) := X"BD";
constant MOVI2R14 : std_logic_vector(7 downto 0) := X"BE";
constant MOVI2R15 : std_logic_vector(7 downto 0) := X"BF";
-----------------------------------------------------------------------------
-- Move Immediate to Register/memory
-----------------------------------------------------------------------------
constant MOVI2RM0 : std_logic_vector(7 downto 0) := X"C6";
constant MOVI2RM1 : std_logic_vector(7 downto 0) := X"C7"; -- Word
-----------------------------------------------------------------------------
-- Segment Register to Register or Memory
-----------------------------------------------------------------------------
constant MOVS2RM : std_logic_vector(7 downto 0) := X"8C";
-----------------------------------------------------------------------------
-- Register or Memory to Segment Register
-----------------------------------------------------------------------------
constant MOVRM2S : std_logic_vector(7 downto 0) := X"8E";
-----------------------------------------------------------------------------
-- Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVM2A0 : std_logic_vector(7 downto 0) := X"A0";
constant MOVM2A1 : std_logic_vector(7 downto 0) := X"A1";
-----------------------------------------------------------------------------
-- Accumulator to Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVA2M0 : std_logic_vector(7 downto 0) := X"A2";
constant MOVA2M1 : std_logic_vector(7 downto 0) := X"A3";
-----------------------------------------------------------------------------
-- Register/Memory to/from Register
-----------------------------------------------------------------------------
constant MOVRM2R0 : std_logic_vector(7 downto 0) := X"88";
constant MOVRM2R1 : std_logic_vector(7 downto 0) := X"89";
constant MOVRM2R2 : std_logic_vector(7 downto 0) := X"8A";
constant MOVRM2R3 : std_logic_vector(7 downto 0) := X"8B";
-----------------------------------------------------------------------------
-- Segment Override Prefix
-----------------------------------------------------------------------------
constant SEGOPES : std_logic_vector(7 downto 0) := X"26";
constant SEGOPCS : std_logic_vector(7 downto 0) := X"2E";
constant SEGOPSS : std_logic_vector(7 downto 0) := X"36";
constant SEGOPDS : std_logic_vector(7 downto 0) := X"3E";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Register/Memory to Register
-----------------------------------------------------------------------------
constant ADDRM2R0 : std_logic_vector(7 downto 0) := X"00";
constant ADDRM2R1 : std_logic_vector(7 downto 0) := X"01";
constant ADDRM2R2 : std_logic_vector(7 downto 0) := X"02";
constant ADDRM2R3 : std_logic_vector(7 downto 0) := X"03";
constant ADCRM2R0 : std_logic_vector(7 downto 0) := X"10";
constant ADCRM2R1 : std_logic_vector(7 downto 0) := X"11";
constant ADCRM2R2 : std_logic_vector(7 downto 0) := X"12";
constant ADCRM2R3 : std_logic_vector(7 downto 0) := X"13";
constant SUBRM2R0 : std_logic_vector(7 downto 0) := X"28";
constant SUBRM2R1 : std_logic_vector(7 downto 0) := X"29";
constant SUBRM2R2 : std_logic_vector(7 downto 0) := X"2A";
constant SUBRM2R3 : std_logic_vector(7 downto 0) := X"2B";
constant SBBRM2R0 : std_logic_vector(7 downto 0) := X"18";
constant SBBRM2R1 : std_logic_vector(7 downto 0) := X"19";
constant SBBRM2R2 : std_logic_vector(7 downto 0) := X"1A";
constant SBBRM2R3 : std_logic_vector(7 downto 0) := X"1B";
constant CMPRM2R0 : std_logic_vector(7 downto 0) := X"38";
constant CMPRM2R1 : std_logic_vector(7 downto 0) := X"39";
constant CMPRM2R2 : std_logic_vector(7 downto 0) := X"3A";
constant CMPRM2R3 : std_logic_vector(7 downto 0) := X"3B";
constant ANDRM2R0 : std_logic_vector(7 downto 0) := X"20";
constant ANDRM2R1 : std_logic_vector(7 downto 0) := X"21";
constant ANDRM2R2 : std_logic_vector(7 downto 0) := X"22";
constant ANDRM2R3 : std_logic_vector(7 downto 0) := X"23";
constant ORRM2R0 : std_logic_vector(7 downto 0) := X"08";
constant ORRM2R1 : std_logic_vector(7 downto 0) := X"09";
constant ORRM2R2 : std_logic_vector(7 downto 0) := X"0A";
constant ORRM2R3 : std_logic_vector(7 downto 0) := X"0B";
constant XORRM2R0 : std_logic_vector(7 downto 0) := X"30";
constant XORRM2R1 : std_logic_vector(7 downto 0) := X"31";
constant XORRM2R2 : std_logic_vector(7 downto 0) := X"32";
constant XORRM2R3 : std_logic_vector(7 downto 0) := X"33";
-----------------------------------------------------------------------------
-- OPCODE 80,81,83, ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate to Reg/Mem
-- Instruction defined in reg field
-----------------------------------------------------------------------------
constant O80I2RM : std_logic_vector(7 downto 0) := X"80";
constant O81I2RM : std_logic_vector(7 downto 0) := X"81";
constant O83I2RM : std_logic_vector(7 downto 0) := X"83";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate with ACCU
-----------------------------------------------------------------------------
constant ADDI2AX0 : std_logic_vector(7 downto 0) := X"04";
constant ADDI2AX1 : std_logic_vector(7 downto 0) := X"05";
constant ADCI2AX0 : std_logic_vector(7 downto 0) := X"14";
constant ADCI2AX1 : std_logic_vector(7 downto 0) := X"15";
constant SUBI2AX0 : std_logic_vector(7 downto 0) := X"2C";
constant SUBI2AX1 : std_logic_vector(7 downto 0) := X"2D";
constant SBBI2AX0 : std_logic_vector(7 downto 0) := X"1C";
constant SBBI2AX1 : std_logic_vector(7 downto 0) := X"1D";
constant CMPI2AX0 : std_logic_vector(7 downto 0) := X"3C";
constant CMPI2AX1 : std_logic_vector(7 downto 0) := X"3D";
constant ANDI2AX0 : std_logic_vector(7 downto 0) := X"24";
constant ANDI2AX1 : std_logic_vector(7 downto 0) := X"25";
constant ORI2AX0 : std_logic_vector(7 downto 0) := X"0C";
constant ORI2AX1 : std_logic_vector(7 downto 0) := X"0D";
constant XORI2AX0 : std_logic_vector(7 downto 0) := X"34";
constant XORI2AX1 : std_logic_vector(7 downto 0) := X"35";
-----------------------------------------------------------------------------
-- TEST (Same as AND but without returning any results)
-----------------------------------------------------------------------------
constant TESTRMR0 : std_logic_vector(7 downto 0) := X"84";
constant TESTRMR1 : std_logic_vector(7 downto 0) := X"85";
constant TESTI2AX0 : std_logic_vector(7 downto 0) := X"A8";
constant TESTI2AX1 : std_logic_vector(7 downto 0) := X"A9";
-----------------------------------------------------------------------------
-- NOT/TEST F6/F7 Shared Instructions
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