pio_rtl.vhd

Run Pac-man Game Based on 8086/8088 FPGA IP Core

-------------------------------------------------------------------------------
--                                                                           --
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005 HT-LAB 												 --
--                                                                           --
-------------------------------------------------------------------------------
--																			 --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Entity Super_IO.pio.rtl
--
-- Created: by - Hans 16/07/2005
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY pio IS
   PORT( 
      clk      : IN     std_logic;
      cspion   : IN     std_logic;
      dbusin   : IN     std_logic_vector (7 DOWNTO 0);
      inport   : IN     std_logic_vector (7 DOWNTO 0);
      resetn   : IN     std_logic;
      wrn      : IN     std_logic;
      dbus_pio : OUT    std_logic_vector (7 DOWNTO 0);
      outport  : OUT    std_logic_vector (7 DOWNTO 0)
   );

-- Declarations

END pio ;


ARCHITECTURE rtl OF pio IS

signal wr_s : std_logic;
--signal rd_s : std_logic;

begin
	
wr_s <= '1' when (cspion='0' AND wrn='0') else '0';
--rd_s <= '1' when (cspion='0' AND rdn='0') else '0';

process (clk,resetn)                  
    begin
        if (resetn='0') then    
        	outport <= (others => '0');                 
      	elsif (rising_edge(clk)) then 
      		if wr_s='1' then
				outport <= dbusin(7 downto 0); 	
			end if;		
		end if;   
end process;

dbus_pio <= inport;
	
END ARCHITECTURE rtl;