embedded_rom.xco

Run Pac-man Game Based on 8086/8088 FPGA IP Core

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\Xilinx\8086vga
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc3s500e
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg320
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3e
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.2
# END Select
# BEGIN Parameters
CSET reset_qspo=false
CSET reset_qdpo=false
CSET coefficient_file=D:/Xilinx/8086vga/rom.coe
CSET dual_port_address=non_registered
CSET common_output_ce=false
CSET memory_type=rom
CSET depth=256
CSET ce_overrides=ce_overrides_sync_controls
CSET data_width=8
CSET pipeline_stages=0
CSET default_data=0
CSET component_name=embedded_rom
CSET single_port_output_clock_enable=false
CSET qualify_we_with_i_ce=false
CSET common_output_clk=false
CSET default_data_radix=16
CSET dual_port_output_clock_enable=false
CSET output_options=non_registered
CSET sync_reset_qspo=false
CSET input_options=registered
CSET sync_reset_qdpo=false
CSET input_clock_enable=false
# END Parameters
GENERATE