lcd_controller.v

基于MAXII CPLD的对1602字符型液晶进行读写操作

/***************************************************************************************************************************************************************
* LCD CONTROLLER
* JANUARY 2007
***************************************************************************************************************************************************************/

`timescale 1 ps / 1 ps

/* TOP MODULE */
module lcd_controller (rst,we,ack,data,DB,RW,RS,E,clk_w);             

input rst,we;                   //we = 1 when writing into LCD  
                                //rst is active low synchronous reset
input [7:0] data;               //data lines from user to LCD controller
inout [7:0] DB;                 //data lines from LCD controller to LCD 
output RW,RS,E,ack,clk_w;       //RS selects command(RS = 0) or data(RS = 1) register of LCD
                                //RW = 1 when reading from LCD and RW = 0 when writing into LCD
wire osc_w, clk_w, data_valid_w,nbusy_w,nread_w;
wire [8:0] addr_w;
wire [7:0] do_w;

fsm fsm(E,clk_w,rst,we,ack,data,DB,RW,RS,addr_w,do_w,data_valid_w,nbusy_w,nread_w); 

UFM2 UFM2(addr_w,nread_w,data_valid_w,do_w,nbusy_w,osc_w); 

divider divider (.osc(osc_w), .clk(clk_w));

endmodule

/************************************************************************************************************
 State Machine Module 
************************************************************************************************************/
`timescale 1 ps / 1 ps
module fsm(E,clk,rst,we,ack,data,DB,RW,RS,addr,data_ufm,data_vin,nbusy,ready); 

input clk,rst,we,data_vin,nbusy;
input [7:0] data,data_ufm; 

inout [7:0] DB;

output ack,RW,RS,E,ready;
output [8:0] addr;

reg RW,RS,E,ack;
reg [7:0] data_in,data_out;
reg [2:0] state;
reg [8:0] addr_reg,addr;
reg [11:0]count1;
reg [2:0] cnt;
reg [2:0] i;
reg dbusy,ready;
reg [7:0] delay;

parameter WAIT = 3'b010,WR_SETUP = 3'b110,RESET_HOLD =3'b011;
parameter WR_HOLD = 3'b111;
parameter RD_SETUP = 3'b101;
parameter RD_HOLD = 3'b100;
parameter ACK = 3'b000;
parameter RESET_SETUP = 3'b001;

bufif0 buffer1 [7:0](DB,data_in,RW); //Tristate buffer

initial 
   begin
       delay = 2'b00;
       i= 2'b00;
       cnt = 3'b000;
       count1 = 12'b000000000000;
       addr_reg =9'b000000000;
       state = 3'b000 ;              //State intialised to acknowledge state
  end
   
always@(posedge clk or negedge rst)
begin
   if(rst == 1'b0)
	   state = RESET_SETUP;
   else if(clk == 1'b1)begin
       case (state)
       WR_SETUP:  // Takes in data to be written into LCD and selects data register in the LCD
	   begin
		   if(rst == 1'b0)begin
		       state = RESET_SETUP;
		   end else begin 
			   ack = 1'b1 ;
			   data_in = data;
			   E=1'b1;
		       RS=1'b1;
		       RW=1'b0;
		       state = WR_HOLD;
		   end
	   end
		
	   WR_HOLD: // Sends negative edge on E to latch data into LCD
	   begin
		  if(rst == 1'b0)begin
		      state = RESET_SETUP;
		  end else begin 
			  E=1'b0;
			  ready =1'b1;
			  state = RD_SETUP;
		  end
	   end
	
	   RD_SETUP : //selects command register in LCD
	   begin
		   if(rst == 1'b0)begin
		   state = RESET_SETUP;
		   end else begin
			   E=1'b1;
			   RS=1'b0;
			   RW=1'b1;
			   state = RD_HOLD;
		   end
	   end
	
	   RD_HOLD: //sends negative edge on E to read data from command register of LCD 
	   begin
		   if(rst == 1'b0)begin
		       state = RESET_SETUP;
		   end else begin
			   E=1'b0;
			   data_out=DB;
			   dbusy = data_out[7];
		       if(dbusy == 1'b0)
			   state = ACK;
			   else	
			   state = RD_SETUP;
		   end
	   end	
	   ACK: //stays in acknowledge state as long as write enable is not asserted
       begin
	   if(rst == 1'b0)begin
	       state = RESET_SETUP;
	   end else begin
			ack = 1'b0;
			if(we == 1'b0)	begin
			    state = WR_SETUP;
			end	else		
			state = ACK;
	   end
       end	
	
       RESET_SETUP: // sets up data to be sent to command register LCD on reset
       begin
       ack = 1'b1;
       if(cnt == 3'b000)begin
		   RS=1'b0;
		   RW=1'b0;
		   E=1'b1;
		   data_in = 8'b00111000; // 0X38
		   state= RESET_HOLD;
	   end else if(cnt == 3'b001)begin
		   E=1'b1;
		   data_in = 8'b00001000; // 0X08
		   state= RESET_HOLD;
	   end else if(cnt == 3'b010)begin
		   E=1'b1;
		   data_in = 8'b00000001; // 0X01
		   state= RESET_HOLD;
	   end else if(cnt == 3'b011)begin
		   E=1'b1;
		   data_in = 8'b00000110; // 0X06
		   state= RESET_HOLD;
	   end else if(cnt == 3'b100)begin
           E=1'b1;
		   data_in = 8'b00001111; // 0X0F
		   state= RESET_HOLD;
	   end else if (addr_reg < 9'b001110001)begin
		   addr = addr_reg;
		   ready = 1'b0;
		   if( data_vin == 1'b1)begin
		   data_in=data_ufm;
		   RS=1'b1;
		   RW=1'b0;
		   E=1'b1;
		   state = RESET_HOLD;
		   end else begin
		   E=1'b0;
		   state = RESET_SETUP;
			end
	   end else if (cnt >= 3'b101)begin
           cnt=3'b000;
		   i = 3'b000;
		   state = ACK;
	   end
       end
       RESET_HOLD: //sends negative edge on LCD and latches data into command register of LCD
       begin
	   E=1'b0;
	   if(cnt < 3'b110)
		  cnt = cnt + 3'b001;
	   if (i <=3'b011) begin
	 	  i = i + 3'b001;
		  cnt = cnt - 3'b001;
	   end	
	   state = WAIT;		
       end			 
       WAIT: // delay state to allow LCD sufficient time for its operation
       begin
	   if(addr_reg < 9'b001110001 && cnt >= 3'b101)	begin
			delay = delay + 8'b00000001;
			if (delay == 8'hE9)begin
				state = RESET_SETUP;
				ready = 1 ;
				delay = 8'b00000000;
				addr_reg = addr_reg + 9'b000000010;
			end
	   end else begin
		   count1 = count1 + 12'b000000000001;
		   if(count1 ==12'h143)begin
		       state = RESET_SETUP;
			   count1 =12'b000000000000;
		   end else
		   state = WAIT;	
	   end
       end
		
       default : 
	   begin
	   end
 
       endcase

    end
end

endmodule

/***************************************************************************************************************************/
`timescale 1 ps / 1 ps

/* Clock divider module */
module divider (osc, clk); 
input osc;
output clk;
reg clk;
reg [6:0]count;

initial
   begin
       count = 7'b0000000;
   end

always @ (posedge(osc))
	begin 
	count = count + 7'b0000001;
	clk = count[6];
	end
endmodule

// megafunction wizard: %Flash Memory%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altufm_parallel 

// ============================================================
// File Name: UFM2.v
// Megafunction Name(s):
// 			altufm_parallel
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
// ************************************************************


//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//altufm_parallel ACCESS_MODE="READ_ONLY" CBX_AUTO_BLACKBOX="ON" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="lcd_new.hex" OSC_FREQUENCY=180000 PROGRAM_TIME=1600000 WIDTH_ADDRESS=9 WIDTH_DATA=8 WIDTH_UFM_ADDRESS=9 addr data_valid do nbusy nread osc
//VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_a_graycounter 2006:03:13:11:03:08:SJ cbx_altufm 2006:03:15:18:56:12:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_maxii 2006:05:15:19:24:18:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


//lpm_counter CBX_AUTO_BLACKBOX="ON" DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_modulus=28 lpm_width=5 clk_en clock q
//VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END

//synthesis_resources = lut 54 maxii_ufm 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  UFM2_altufm_parallel_bmm
	( 
	addr,
	data_valid,
	do,
	nbusy,
	nread,
	osc) /* synthesis synthesis_clearbox=1 */;
	input   [8:0]  addr;
	output   data_valid;
	output   [7:0]  do;
	output   nbusy;
	input   nread;
	output   osc;

	reg	[0:0]	dffe10a0;
	reg	[0:0]	dffe10a1;
	reg	[0:0]	dffe10a2;
	reg	[0:0]	dffe10a3;
	reg	[0:0]	dffe10a4;
	reg	[0:0]	dffe10a5;
	reg	[0:0]	dffe10a6;
	reg	[0:0]	dffe10a7;
	reg	[0:0]	dffe10a8;
	reg	[0:0]	dffe10a9;
	reg	[0:0]	dffe10a10;
	reg	[0:0]	dffe10a11;
	reg	[0:0]	dffe10a12;
	reg	[0:0]	dffe10a13;
	reg	[0:0]	dffe10a14;
	reg	[0:0]	dffe10a15;
	reg	[7:0]	dffe11a;
	wire	wire_dffe11a_ENA;
	reg	dffe12;
	reg	dffe13;
	reg	dffe2;
	reg	dffe3;
	reg	dffe4;
	reg	dffe5;
	reg	dffe7;
	reg	dffe8;
	reg	[8:0]	dffe9a;
	reg	[5:0]	wire_cntr6_q_int;
	wire	wire_cntr6_clk_en;
	wire	wire_cntr6_clock;
	wire	[4:0]	wire_cntr6_q;
	wire  wire_maxii_ufm_block1_bgpbusy;
	wire  wire_maxii_ufm_block1_drdout;
	wire  wire_maxii_ufm_block1_osc;
	wire  add_en;
	wire  add_load;
	wire  arclk;
	wire  busy_arclk;
	wire  busy_drclk;
	wire  control_mux;
	wire  copy_tmp_decode;
	wire  data_valid_en;
	wire  dly_tmp_decode;
	wire  drdin;
	wire  gated1;
	wire  gated2;
	wire  hold_decode;
	wire  in_read_data_en;
	wire  in_read_drclk;
	wire  in_read_drshft;
	wire  mux_nread;
	wire  q0;
	wire  q1;
	wire  q2;
	wire  q3;
	wire  q4;
	wire  read;
	wire  read_op;
	wire  real_decode;
	wire  [8:0]  shiftin;
	wire  [15:0]  sipo_q;
	wire  start_decode;
	wire  start_op;
	wire  stop_op;
	wire  tmp_add_en;
	wire  tmp_add_load;
	wire  tmp_arclk;
	wire  tmp_arclk0;
	wire  tmp_ardin;
	wire  tmp_arshft;
	wire  tmp_data_valid2;
	wire  tmp_decode;
	wire  tmp_drclk;
	wire  tmp_in_read_data_en;
	wire  tmp_in_read_drclk;
	wire  tmp_in_read_drshft;
	wire  tmp_read;