fx2_to_extsram.c

和LA_USB配套使用,USB 固件部分,对学习FX2有一定帮助

{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}

#define VX_B1 0xB1
#define VX_B2 0xB2 		// run/stop/pause
#define VX_B3 0xB3 		// soft reset
#define VX_B4 0xB4 		// system status
#define CMD_RUN 0xAA 	// run  command
#define CMD_PAUSE 0x05 	// pause	command
#define CMD_CTNU 0x0A 	// continue command
#define CMD_STOP 0x55 	// stop command

BOOL DR_VendorCmnd(void)
{
	WORD Master_req;
    switch (SETUPDAT[1])
  {
    case VX_B2:		  // RUN/STOP DO
    { 

		Master_req = SETUPDAT[2];
		SYNCDELAY;
		switch(SETUPDAT[2])
		{
			case  CMD_RUN: 	out_enable = TRUE;		//DO_RUN_OUT=1(IOA.1)
							IOA |=0x02;
							SYNCDELAY;
							IOA &=0xFD;
							break;
	
			case  CMD_STOP:	OUT_STOP_FLAG = TRUE;
							break;
			default: break;
		}
			*EP0BUF = VX_B2;  
		*(EP0BUF+1) = SETUPDAT[2];  
		*(EP0BUF+2) = SETUPDAT[3];  
		EP0BCH = 0;
		EP0BCL = 3;                   // Arm endpoint with # bytes to transfer
		EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
		break;
	
	 }

	 case VX_B1:
	   {	   	Master_req = SETUPDAT[2];
		        SYNCDELAY;
		        switch(SETUPDAT[2])
	
	
		{ 
			case  CMD_RUN: 	
							IOA |=0x04;
							SYNCDELAY;
							IOA &=0xFB;
							in_enable = TRUE;		//DO_RUN_IN=1(IOA.2)
							break;
	
			case  CMD_STOP:	IN_STOP_FLAG = TRUE;
							break;
			default: break;
		}

		*EP0BUF = VX_B1;  
		*(EP0BUF+1) = SETUPDAT[2];  
		*(EP0BUF+2) = SETUPDAT[3];  
		EP0BCH = 0;
		EP0BCL = 3;                   // Arm endpoint with # bytes to transfer
		EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
		break;
 		}
   
    case VX_B3:		   //RESET CPLD
    { 
		IOA &= 0xEF;     // SF_RST=0  (IOA.4)
		SYNCDELAY;
		SYNCDELAY;
		IOA |= 0x10;     // SF_RST=1  (IOA.4)
		
		*EP0BUF = VX_B3;  
		EP0BCH = 0;
		EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
		EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
		break;
	 }
    case VX_B4:		   //SYSTEM STATUS
    { 
		*EP0BUF = VX_B4;  
		*(EP0BUF+1) = (IOA>>4);  
		EP0BCH = 0;
		EP0BCL = 2;                   // Arm endpoint with # bytes to transfer
		EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
		break;
	 }
     default:
        return(TRUE);
  }

  return(FALSE);
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
   GotSUD = TRUE;            // Set flag
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ
}

void ISR_Sof(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSOF;            // Clear SOF IRQ
}

void ISR_Ures(void) interrupt 0
{
   // whenever we get a USB reset, we should revert to full speed mode
   pConfigDscr = pFullSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
   pOtherConfigDscr = pHighSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmURES;         // Clear URES IRQ
}

void ISR_Susp(void) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
      pOtherConfigDscr = pFullSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
   }

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}

void Setup_FLOWSTATE_Read ( void )
{
   FLOWSTATE = FlowStates[18];  // 1000 0011b - FSE=1, FS[2:0]=003
   SYNCDELAY;
   FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
   SYNCDELAY;
   FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
   SYNCDELAY;
}

void Setup_FLOWSTATE_Write ( void )
{ 
   FLOWSTATE = FlowStates[27];  // 1000 0001b - FSE=1, FS[2:0]=001
   SYNCDELAY;
   FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
   SYNCDELAY;
   FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
   SYNCDELAY;
}