📄 fx2_to_extsram.lst
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303 1 }
304
305 BOOL DR_ClearFeature(void)
306 {
307 1 return(TRUE);
308 1 }
309
310 BOOL DR_SetFeature(void)
311 {
312 1 return(TRUE);
313 1 }
314
315 #define VX_B1 0xB1
316 #define VX_B2 0xB2 // run/stop/pause
317 #define VX_B3 0xB3 // soft reset
318 #define VX_B4 0xB4 // system status
319 #define CMD_RUN 0xAA // run command
320 #define CMD_PAUSE 0x05 // pause command
321 #define CMD_CTNU 0x0A // continue command
322 #define CMD_STOP 0x55 // stop command
323
324 BOOL DR_VendorCmnd(void)
325 {
326 1 WORD Master_req;
327 1 switch (SETUPDAT[1])
328 1 {
329 2 case VX_B2: // RUN/STOP DO
330 2 {
331 3
332 3 Master_req = SETUPDAT[2];
333 3 SYNCDELAY;
334 3 switch(SETUPDAT[2])
335 3 {
336 4 case CMD_RUN: out_enable = TRUE; //DO_RUN_OUT=1(IOA.1)
337 4 IOA |=0x02;
338 4 SYNCDELAY;
339 4 IOA &=0xFD;
340 4 break;
341 4
342 4 case CMD_STOP: OUT_STOP_FLAG = TRUE;
343 4 break;
344 4 default: break;
345 4 }
346 3 *EP0BUF = VX_B2;
347 3 *(EP0BUF+1) = SETUPDAT[2];
348 3 *(EP0BUF+2) = SETUPDAT[3];
349 3 EP0BCH = 0;
350 3 EP0BCL = 3; // Arm endpoint with # bytes to transfer
351 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
352 3 break;
353 3
354 3 }
355 2
356 2 case VX_B1:
357 2 { Master_req = SETUPDAT[2];
358 3 SYNCDELAY;
359 3 switch(SETUPDAT[2])
360 3
361 3
362 3 {
363 4 case CMD_RUN:
364 4 IOA |=0x04;
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 7
365 4 SYNCDELAY;
366 4 IOA &=0xFB;
367 4 in_enable = TRUE; //DO_RUN_IN=1(IOA.2)
368 4 break;
369 4
370 4 case CMD_STOP: IN_STOP_FLAG = TRUE;
371 4 break;
372 4 default: break;
373 4 }
374 3
375 3 *EP0BUF = VX_B1;
376 3 *(EP0BUF+1) = SETUPDAT[2];
377 3 *(EP0BUF+2) = SETUPDAT[3];
378 3 EP0BCH = 0;
379 3 EP0BCL = 3; // Arm endpoint with # bytes to transfer
380 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
381 3 break;
382 3 }
383 2
384 2 case VX_B3: //RESET CPLD
385 2 {
386 3 IOA &= 0xEF; // SF_RST=0 (IOA.4)
387 3 SYNCDELAY;
388 3 SYNCDELAY;
389 3 IOA |= 0x10; // SF_RST=1 (IOA.4)
390 3
391 3 *EP0BUF = VX_B3;
392 3 EP0BCH = 0;
393 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
394 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
395 3 break;
396 3 }
397 2 case VX_B4: //SYSTEM STATUS
398 2 {
399 3 *EP0BUF = VX_B4;
400 3 *(EP0BUF+1) = (IOA>>4);
401 3 EP0BCH = 0;
402 3 EP0BCL = 2; // Arm endpoint with # bytes to transfer
403 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
404 3 break;
405 3 }
406 2 default:
407 2 return(TRUE);
408 2 }
409 1
410 1 return(FALSE);
411 1 }
412
413 //-----------------------------------------------------------------------------
414 // USB Interrupt Handlers
415 // The following functions are called by the USB interrupt jump table.
416 //-----------------------------------------------------------------------------
417
418 // Setup Data Available Interrupt Handler
419 void ISR_Sudav(void) interrupt 0
420 {
421 1 GotSUD = TRUE; // Set flag
422 1 EZUSB_IRQ_CLEAR();
423 1 USBIRQ = bmSUDAV; // Clear SUDAV IRQ
424 1 }
425
426 // Setup Token Interrupt Handler
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 8
427 void ISR_Sutok(void) interrupt 0
428 {
429 1 EZUSB_IRQ_CLEAR();
430 1 USBIRQ = bmSUTOK; // Clear SUTOK IRQ
431 1 }
432
433 void ISR_Sof(void) interrupt 0
434 {
435 1 EZUSB_IRQ_CLEAR();
436 1 USBIRQ = bmSOF; // Clear SOF IRQ
437 1 }
438
439 void ISR_Ures(void) interrupt 0
440 {
441 1 // whenever we get a USB reset, we should revert to full speed mode
442 1 pConfigDscr = pFullSpeedConfigDscr;
443 1 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
444 1 pOtherConfigDscr = pHighSpeedConfigDscr;
445 1 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
446 1
447 1 EZUSB_IRQ_CLEAR();
448 1 USBIRQ = bmURES; // Clear URES IRQ
449 1 }
450
451 void ISR_Susp(void) interrupt 0
452 {
453 1 Sleep = TRUE;
454 1 EZUSB_IRQ_CLEAR();
455 1 USBIRQ = bmSUSP;
456 1 }
457
458 void ISR_Highspeed(void) interrupt 0
459 {
460 1 if (EZUSB_HIGHSPEED())
461 1 {
462 2 pConfigDscr = pHighSpeedConfigDscr;
463 2 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
464 2 pOtherConfigDscr = pFullSpeedConfigDscr;
465 2 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
466 2 }
467 1
468 1 EZUSB_IRQ_CLEAR();
469 1 USBIRQ = bmHSGRANT;
470 1 }
471 void ISR_Ep0ack(void) interrupt 0
472 {
473 1 }
474 void ISR_Stub(void) interrupt 0
475 {
476 1 }
477 void ISR_Ep0in(void) interrupt 0
478 {
479 1 }
480 void ISR_Ep0out(void) interrupt 0
481 {
482 1 }
483 void ISR_Ep1in(void) interrupt 0
484 {
485 1 }
486 void ISR_Ep1out(void) interrupt 0
487 {
488 1 }
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 9
489 void ISR_Ep2inout(void) interrupt 0
490 {
491 1 }
492 void ISR_Ep4inout(void) interrupt 0
493 {
494 1 }
495 void ISR_Ep6inout(void) interrupt 0
496 {
497 1 }
498 void ISR_Ep8inout(void) interrupt 0
499 {
500 1 }
501 void ISR_Ibn(void) interrupt 0
502 {
503 1 }
504 void ISR_Ep0pingnak(void) interrupt 0
505 {
506 1 }
507 void ISR_Ep1pingnak(void) interrupt 0
508 {
509 1 }
510 void ISR_Ep2pingnak(void) interrupt 0
511 {
512 1 }
513 void ISR_Ep4pingnak(void) interrupt 0
514 {
515 1 }
516 void ISR_Ep6pingnak(void) interrupt 0
517 {
518 1 }
519 void ISR_Ep8pingnak(void) interrupt 0
520 {
521 1 }
522 void ISR_Errorlimit(void) interrupt 0
523 {
524 1 }
525 void ISR_Ep2piderror(void) interrupt 0
526 {
527 1 }
528 void ISR_Ep4piderror(void) interrupt 0
529 {
530 1 }
531 void ISR_Ep6piderror(void) interrupt 0
532 {
533 1 }
534 void ISR_Ep8piderror(void) interrupt 0
535 {
536 1 }
537 void ISR_Ep2pflag(void) interrupt 0
538 {
539 1 }
540 void ISR_Ep4pflag(void) interrupt 0
541 {
542 1 }
543 void ISR_Ep6pflag(void) interrupt 0
544 {
545 1 }
546 void ISR_Ep8pflag(void) interrupt 0
547 {
548 1 }
549 void ISR_Ep2eflag(void) interrupt 0
550 {
C51 COMPILER V7.50 FX2_TO_EXTSRAM 11/28/2006 14:33:42 PAGE 10
551 1 }
552 void ISR_Ep4eflag(void) interrupt 0
553 {
554 1 }
555 void ISR_Ep6eflag(void) interrupt 0
556 {
557 1 }
558 void ISR_Ep8eflag(void) interrupt 0
559 {
560 1 }
561 void ISR_Ep2fflag(void) interrupt 0
562 {
563 1 }
564 void ISR_Ep4fflag(void) interrupt 0
565 {
566 1 }
567 void ISR_Ep6fflag(void) interrupt 0
568 {
569 1 }
570 void ISR_Ep8fflag(void) interrupt 0
571 {
572 1 }
573 void ISR_GpifComplete(void) interrupt 0
574 {
575 1 }
576 void ISR_GpifWaveform(void) interrupt 0
577 {
578 1 }
579
580 void Setup_FLOWSTATE_Read ( void )
581 {
582 1 FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
583 1 SYNCDELAY;
584 1 FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
585 1 SYNCDELAY;
586 1 FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
587 1 SYNCDELAY;
588 1 }
589
590 void Setup_FLOWSTATE_Write ( void )
591 {
592 1 FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001
593 1 SYNCDELAY;
594 1 FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
595 1 SYNCDELAY;
596 1 FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
597 1 SYNCDELAY;
598 1 }
599
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 988 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 29 2
IDATA SIZE = ---- ----
BIT SIZE = 6 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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