en_blk.vhd

来自「implemention of FPGA and DSP linking por」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY en_blk IS
	PORT(
			CS			:	IN 	STD_LOGIC;
			Addr		:	IN	STD_LOGIC_VECTOR(1 DOWNTO 0);
			eno			:	OUT	STD_LOGIC;
			To_DSP_En	:	OUT	STD_LOGIC;
			From_DSP_En	:	OUT	STD_LOGIC
		);
END en_blk;

ARCHITECTURE ARC OF en_blk IS
BEGIN
	eno <= '1' WHEN CS='0' AND Addr="10" ELSE
		  '0';	
	From_DSP_En <= '1' WHEN CS='0' AND Addr="00" ELSE
		  '0';	
	To_DSP_En <= '1' WHEN (CS='0' AND (Addr="01" OR Addr="10" OR Addr="11")) ELSE
		  '0';	
		
END ARC;