fpga_dsp_portlink.tan.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "RE register FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\] register FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\] 156.05 MHz 6.408 ns Internal " "Info: Clock \"RE\" has Internal fmax of 156.05 MHz between source register \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\]\" and destination register \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\]\" (period= 6.408 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.125 ns + Longest register register " "Info: + Longest register to register delay is 6.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\] 1 REG LCFF_X22_Y8_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y8_N9; Fanout = 1; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } "NODE_NAME" } "" } } { "db/dffpipe_b09.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dffpipe_b09.tdf" 32 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.618 ns) + CELL(0.512 ns) 1.130 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~72 2 COMB LCCOMB_X22_Y8_N12 1 " "Info: 2: + IC(0.618 ns) + CELL(0.512 ns) = 1.130 ns; Loc. = LCCOMB_X22_Y8_N12; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~72'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.130 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.317 ns) + CELL(0.512 ns) 1.959 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~75 3 COMB LCCOMB_X22_Y8_N26 1 " "Info: 3: + IC(0.317 ns) + CELL(0.512 ns) = 1.959 ns; Loc. = LCCOMB_X22_Y8_N26; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~75'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.829 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.295 ns) + CELL(0.521 ns) 2.775 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~0 4 COMB LCCOMB_X22_Y8_N14 3 " "Info: 4: + IC(0.295 ns) + CELL(0.521 ns) = 2.775 ns; Loc. = LCCOMB_X22_Y8_N14; Fanout = 3; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdempty_eq_comp_aeb_int~0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.816 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.322 ns) 3.413 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdcnt_addr_ena 5 COMB LCCOMB_X22_Y8_N16 92 " "Info: 5: + IC(0.316 ns) + CELL(0.322 ns) = 3.413 ns; Loc. = LCCOMB_X22_Y8_N16; Fanout = 92; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdcnt_addr_ena'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.638 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 72 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.517 ns) 4.757 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera0~COUT 6 COMB LCCOMB_X23_Y8_N8 2 " "Info: 6: + IC(0.827 ns) + CELL(0.517 ns) = 4.757 ns; Loc. = LCCOMB_X23_Y8_N8; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera0~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.344 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.837 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera1~COUT 7 COMB LCCOMB_X23_Y8_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.837 ns; Loc. = LCCOMB_X23_Y8_N10; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera1~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.917 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera2~COUT 8 COMB LCCOMB_X23_Y8_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.917 ns; Loc. = LCCOMB_X23_Y8_N12; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera2~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 5.091 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera3~COUT 9 COMB LCCOMB_X23_Y8_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.174 ns) = 5.091 ns; Loc. = LCCOMB_X23_Y8_N14; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera3~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.174 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 50 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.171 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera4~COUT 10 COMB LCCOMB_X23_Y8_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 5.171 ns; Loc. = LCCOMB_X23_Y8_N16; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera4~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 55 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.251 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera5~COUT 11 COMB LCCOMB_X23_Y8_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 5.251 ns; Loc. = LCCOMB_X23_Y8_N18; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera5~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 60 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.331 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera6~COUT 12 COMB LCCOMB_X23_Y8_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 5.331 ns; Loc. = LCCOMB_X23_Y8_N20; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera6~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.411 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera7~COUT 13 COMB LCCOMB_X23_Y8_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 5.411 ns; Loc. = LCCOMB_X23_Y8_N22; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera7~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 70 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.491 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera8~COUT 14 COMB LCCOMB_X23_Y8_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 5.491 ns; Loc. = LCCOMB_X23_Y8_N24; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera8~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 75 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.571 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera9~COUT 15 COMB LCCOMB_X23_Y8_N26 1 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 5.571 ns; Loc. = LCCOMB_X23_Y8_N26; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera9~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.080 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 6.029 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera10 16 COMB LCCOMB_X23_Y8_N28 1 " "Info: 16: + IC(0.000 ns) + CELL(0.458 ns) = 6.029 ns; Loc. = LCCOMB_X23_Y8_N28; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|countera10'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.458 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 85 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.125 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\] 17 REG LCFF_X23_Y8_N29 10 " "Info: 17: + IC(0.000 ns) + CELL(0.096 ns) = 6.125 ns; Loc. = LCFF_X23_Y8_N29; Fanout = 10; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.096 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 96 31 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.752 ns ( 61.26 % ) " "Info: Total cell delay = 3.752 ns ( 61.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.373 ns ( 38.74 % ) " "Info: Total interconnect delay = 2.373 ns ( 38.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "6.125 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.125 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } { 0.000ns 0.618ns 0.317ns 0.295ns 0.316ns 0.827ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.512ns 0.512ns 0.521ns 0.322ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.044 ns - Smallest " "Info: - Smallest clock skew is -0.044 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RE destination 3.030 ns + Shortest register " "Info: + Shortest clock path from clock \"RE\" to destination register is 3.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.784 ns) 0.784 ns RE 1 CLK PIN_116 151 " "Info: 1: + IC(0.000 ns) + CELL(0.784 ns) = 0.784 ns; Loc. = PIN_116; Fanout = 151; CLK Node = 'RE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { RE } "NODE_NAME" } "" } } { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 328 -72 96 344 "RE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.644 ns) + CELL(0.602 ns) 3.030 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\] 2 REG LCFF_X23_Y8_N29 10 " "Info: 2: + IC(1.644 ns) + CELL(0.602 ns) = 3.030 ns; Loc. = LCFF_X23_Y8_N29; Fanout = 10; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\|power_modified_counter_values\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "2.246 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 96 31 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.386 ns ( 45.74 % ) " "Info: Total cell delay = 1.386 ns ( 45.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.644 ns ( 54.26 % ) " "Info: Total interconnect delay = 1.644 ns ( 54.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.030 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.030 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } { 0.000ns 0.000ns 1.644ns } { 0.000ns 0.784ns 0.602ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RE source 3.074 ns - Longest register " "Info: - Longest clock path from clock \"RE\" to source register is 3.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.784 ns) 0.784 ns RE 1 CLK PIN_116 151 " "Info: 1: + IC(0.000 ns) + CELL(0.784 ns) = 0.784 ns; Loc. = PIN_116; Fanout = 151; CLK Node = 'RE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { RE } "NODE_NAME" } "" } } { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 328 -72 96 344 "RE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.602 ns) 3.074 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\] 2 REG LCFF_X22_Y8_N9 1 " "Info: 2: + IC(1.688 ns) + CELL(0.602 ns) = 3.074 ns; Loc. = LCFF_X22_Y8_N9; Fanout = 1; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\|dffe7a\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "2.290 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } "NODE_NAME" } "" } } { "db/dffpipe_b09.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dffpipe_b09.tdf" 32 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.386 ns ( 45.09 % ) " "Info: Total cell delay = 1.386 ns ( 45.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.688 ns ( 54.91 % ) " "Info: Total interconnect delay = 1.688 ns ( 54.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.074 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.074 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.784ns 0.602ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.030 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.030 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } { 0.000ns 0.000ns 1.644ns } { 0.000ns 0.784ns 0.602ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.074 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.074 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.784ns 0.602ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "db/dffpipe_b09.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dffpipe_b09.tdf" 32 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 96 31 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "6.125 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.125 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } { 0.000ns 0.618ns 0.317ns 0.295ns 0.316ns 0.827ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.512ns 0.512ns 0.521ns 0.322ns 0.517ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.030 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.030 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10] } { 0.000ns 0.000ns 1.644ns } { 0.000ns 0.784ns 0.602ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.074 ns" { RE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.074 ns" { RE RE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.784ns 0.602ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "WE register FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\] memory FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg 132.59 MHz 7.542 ns Internal " "Info: Clock \"WE\" has Internal fmax of 132.59 MHz between source register \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\]\" and destination memory \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg\" (period= 7.542 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.079 ns + Longest register memory " "Info: + Longest register to memory delay is 7.079 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\] 1 REG LCFF_X19_Y5_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 3; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 95 31 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.544 ns) 1.798 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~79 2 COMB LCCOMB_X22_Y8_N30 1 " "Info: 2: + IC(1.254 ns) + CELL(0.544 ns) = 1.798 ns; Loc. = LCCOMB_X22_Y8_N30; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~79'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.798 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.512 ns) 3.493 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~81 3 COMB LCCOMB_X19_Y5_N4 1 " "Info: 3: + IC(1.183 ns) + CELL(0.512 ns) = 3.493 ns; Loc. = LCCOMB_X19_Y5_N4; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~81'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.695 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.491 ns) 4.281 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~0 4 COMB LCCOMB_X19_Y5_N2 2 " "Info: 4: + IC(0.297 ns) + CELL(0.491 ns) = 4.281 ns; Loc. = LCCOMB_X19_Y5_N2; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.788 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.312 ns) + CELL(0.178 ns) 4.771 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|valid_wrreq 5 COMB LCCOMB_X19_Y5_N0 23 " "Info: 5: + IC(0.312 ns) + CELL(0.178 ns) = 4.771 ns; Loc. = LCCOMB_X19_Y5_N0; Fanout = 23; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|valid_wrreq'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.490 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 74 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.958 ns) + CELL(0.350 ns) 7.079 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg 6 MEM M4K_X11_Y7 0 " "Info: 6: + IC(1.958 ns) + CELL(0.350 ns) = 7.079 ns; Loc. = M4K_X11_Y7; Fanout = 0; MEM Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "2.308 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_uk61.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/altsyncram_uk61.tdf" 145 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.075 ns ( 29.31 % ) " "Info: Total cell delay = 2.075 ns ( 29.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.004 ns ( 70.69 % ) " "Info: Total interconnect delay = 5.004 ns ( 70.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "7.079 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "7.079 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } { 0.000ns 1.254ns 1.183ns 0.297ns 0.312ns 1.958ns } { 0.000ns 0.544ns 0.512ns 0.491ns 0.178ns 0.350ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.146 ns - Smallest " "Info: - Smallest clock skew is -0.146 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WE destination 3.189 ns + Shortest memory " "Info: + Shortest clock path from clock \"WE\" to destination memory is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.784 ns) 0.784 ns WE 1 CLK PIN_118 184 " "Info: 1: + IC(0.000 ns) + CELL(0.784 ns) = 0.784 ns; Loc. = PIN_118; Fanout = 184; CLK Node = 'WE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { WE } "NODE_NAME" } "" } } { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 280 -72 96 296 "WE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(0.783 ns) 3.189 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg 2 MEM M4K_X11_Y7 0 " "Info: 2: + IC(1.622 ns) + CELL(0.783 ns) = 3.189 ns; Loc. = M4K_X11_Y7; Fanout = 0; MEM Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\|ram_block4a3~portb_we_reg'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "2.405 ns" { WE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_uk61.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/altsyncram_uk61.tdf" 145 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.567 ns ( 49.14 % ) " "Info: Total cell delay = 1.567 ns ( 49.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.622 ns ( 50.86 % ) " "Info: Total interconnect delay = 1.622 ns ( 50.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "3.189 ns" { WE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.189 ns" { WE WE~combout FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg } { 0.000ns 0.000ns 1.622ns } { 0.000ns 0.784ns 0.783ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WE source 3.335 ns - Longest register " "Info: - Longest clock path from clock \"WE\" to source register is 3.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.784 ns) 0.784 ns WE 1 CLK PIN_118 184 " "Info: 1: + IC(0.000 ns) + CELL(0.784 ns) = 0.784 ns; Loc. = PIN_118; Fanout = 184; CLK Node = 'WE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { WE } "NODE_NAME" } "" } } { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 280 -72 96 296 "WE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.949 ns) + CELL(0.602 ns) 3.335 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\] 2 REG LCFF_X19_Y5_N29 3 " "Info: 2: + IC(1.949 ns) + CELL(0.602 ns) = 3.335 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 3; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[9\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "2.551 ns" { WE FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 95 31 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.386 ns ( 41.56 % ) " "Info: Total cell delay = 1.386 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.949 ns ( 58.44 % ) " "Info: Total interconnect delay = 1.949 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_