fpga_dsp_portlink.hif

implemention of FPGA and DSP linking port, using Asynchronous mode

# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(78).cnf
db|FPGA_DSP_PortLink.(78).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
2048
PARAMETER_DEC
USR
LPM_WIDTHU
11
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_fe71
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component
}
# end
# entity
dcfifo_fe71
# storage
db|FPGA_DSP_PortLink.(79).cnf
db|FPGA_DSP_PortLink.(79).cnf
# case_insensitive
# source_file
db|dcfifo_fe71.tdf
ebe3be882c6d4f5ff578d28c6afc0b2
6
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated
}
# end
# entity
a_graycounter_p96
# storage
db|FPGA_DSP_PortLink.(80).cnf
db|FPGA_DSP_PortLink.(80).cnf
# case_insensitive
# source_file
db|a_graycounter_p96.tdf
9ec28c54f534b26c93622730933cb8a1
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p
}
# end
# entity
a_graycounter_ik6
# storage
db|FPGA_DSP_PortLink.(81).cnf
db|FPGA_DSP_PortLink.(81).cnf
# case_insensitive
# source_file
db|a_graycounter_ik6.tdf
44dab4afac9ff47331d908051db1b
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p
}
# end
# entity
altsyncram_ofr
# storage
db|FPGA_DSP_PortLink.(82).cnf
db|FPGA_DSP_PortLink.(82).cnf
# case_insensitive
# source_file
db|altsyncram_ofr.tdf
953b3f89034eef6a9411024b56535e
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram
}
# end
# entity
altsyncram_uk61
# storage
db|FPGA_DSP_PortLink.(83).cnf
db|FPGA_DSP_PortLink.(83).cnf
# case_insensitive
# source_file
db|altsyncram_uk61.tdf
dd5cdff98d6ad7b6f577d69bc313f856
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
addressstall_a
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
none
0
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3
}
# end
# entity
alt_synch_pipe_hv7
# storage
db|FPGA_DSP_PortLink.(84).cnf
db|FPGA_DSP_PortLink.(84).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_hv7.tdf
c14c2ffeb7ddc545845a042c0cbc871
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp
}
# end
# entity
dffpipe_b09
# storage
db|FPGA_DSP_PortLink.(85).cnf
db|FPGA_DSP_PortLink.(85).cnf
# case_insensitive
# source_file
db|dffpipe_b09.tdf
a3cfcd78a0281b1cadef1111b9ac8df8
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5
}
# end
# entity
alt_synch_pipe_iv7
# storage
db|FPGA_DSP_PortLink.(86).cnf
db|FPGA_DSP_PortLink.(86).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_iv7.tdf
8bbc39e378cf4c35afad8ae40d04b9
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp
}
# end
# entity
dffpipe_c09
# storage
db|FPGA_DSP_PortLink.(87).cnf
db|FPGA_DSP_PortLink.(87).cnf
# case_insensitive
# source_file
db|dffpipe_c09.tdf
ca58acaeaf11c52cc5bab363b5793fe
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8
}
# end
# entity
lpm_bustri1
# storage
db|FPGA_DSP_PortLink.(88).cnf
db|FPGA_DSP_PortLink.(88).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_bustri1.vhd
28bf5fc297833f788ddb11ed42a5a4c
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_bustri1:inst4
}
# end
# entity
lpm_bustri
# storage
db|FPGA_DSP_PortLink.(89).cnf
db|FPGA_DSP_PortLink.(89).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|lpm_bustri.tdf
ed9464e1998de88a81948be961c1d04b
6
# user_parameter {
LPM_WIDTH
16
PARAMETER_DEC
USR
}
# used_port {
tridata9
-1
3
tridata8
-1
3
tridata7
-1
3
tridata6
-1
3
tridata5
-1
3
tridata4
-1
3
tridata3
-1
3
tridata2
-1
3
tridata15
-1
3
tridata14
-1
3
tridata13
-1
3
tridata12
-1
3
tridata11
-1
3
tridata10
-1
3
tridata1
-1
3
tridata0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
enabletr
-1
3
enabledt
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component
}
# end
# entity
FIFO_RDN_ByDSP
# storage
db|FPGA_DSP_PortLink.(90).cnf
db|FPGA_DSP_PortLink.(90).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
FIFO_RDN_ByDSP.vhd
33d6bce85c7a86f9f15b878cd78bf68
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
FIFO_RDN_ByDSP:inst5
}
# end
# entity
FPGA_DSP_PortLink_BiBus
# storage
db|FPGA_DSP_PortLink.(75).cnf
db|FPGA_DSP_PortLink.(75).cnf
# case_insensitive
# source_file
FPGA_DSP_PortLink_BiBus.bdf
64ddd654e7d8c3292fa65a6c791bd2
23
# end
# entity
en_blk
# storage
db|FPGA_DSP_PortLink.(76).cnf
db|FPGA_DSP_PortLink.(76).cnf
# logic_op