fpga_dsp_portlink.hif

implemention of FPGA and DSP linking port, using Asynchronous mode

# storage
db|FPGA_DSP_PortLink.(54).cnf
db|FPGA_DSP_PortLink.(54).cnf
# case_insensitive
# source_file
db|dcfifo_aba1.tdf
932e234f611bdf5acbed6150d9eee
6
# used_port {
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrempty
-1
3
wrclk
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdfull
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
a_gray2bin_7cb
# storage
db|FPGA_DSP_PortLink.(55).cnf
db|FPGA_DSP_PortLink.(55).cnf
# case_insensitive
# source_file
db|a_gray2bin_7cb.tdf
41c9c436a8696a4df410a79b94164f
6
# used_port {
gray3
-1
3
gray2
-1
3
gray1
-1
3
gray0
-1
3
bin3
-1
3
bin2
-1
3
bin1
-1
3
bin0
-1
3
}
# end
# entity
a_graycounter_b86
# storage
db|FPGA_DSP_PortLink.(56).cnf
db|FPGA_DSP_PortLink.(56).cnf
# case_insensitive
# source_file
db|a_graycounter_b86.tdf
9c663283f0d67c50fdf74083ed6bfb44
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
a_graycounter_4j6
# storage
db|FPGA_DSP_PortLink.(57).cnf
db|FPGA_DSP_PortLink.(57).cnf
# case_insensitive
# source_file
db|a_graycounter_4j6.tdf
4b9e674c27c1fb15ce998983d649862
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
altsyncram_scr
# storage
db|FPGA_DSP_PortLink.(58).cnf
db|FPGA_DSP_PortLink.(58).cnf
# case_insensitive
# source_file
db|altsyncram_scr.tdf
8f4d374384ccceed717f11cf2a2802c
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
alt_synch_pipe_497
# storage
db|FPGA_DSP_PortLink.(59).cnf
db|FPGA_DSP_PortLink.(59).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_497.tdf
6c694313a684a5e46dc8968937efd0
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_u98
# storage
db|FPGA_DSP_PortLink.(60).cnf
db|FPGA_DSP_PortLink.(60).cnf
# case_insensitive
# source_file
db|dffpipe_u98.tdf
6a5db9d69227b58846628b505a5d06f
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_1v8
# storage
db|FPGA_DSP_PortLink.(61).cnf
db|FPGA_DSP_PortLink.(61).cnf
# case_insensitive
# source_file
db|dffpipe_1v8.tdf
d44d106339a9cff26f7eb995918185c7
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_7u7
# storage
db|FPGA_DSP_PortLink.(62).cnf
db|FPGA_DSP_PortLink.(62).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_7u7.tdf
da7c422f31ee90879f3cf9d538e5958a
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_2v8
# storage
db|FPGA_DSP_PortLink.(63).cnf
db|FPGA_DSP_PortLink.(63).cnf
# case_insensitive
# source_file
db|dffpipe_2v8.tdf
a935883a85821d3c2ee13dfe5781c5e
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_597
# storage
db|FPGA_DSP_PortLink.(64).cnf
db|FPGA_DSP_PortLink.(64).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_597.tdf
c97dc339a6e677a7d4ab2e94a5dcf57
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_v98
# storage
db|FPGA_DSP_PortLink.(65).cnf
db|FPGA_DSP_PortLink.(65).cnf
# case_insensitive
# source_file
db|dffpipe_v98.tdf
9f13372ede5125bc9aa71fa76f699b
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_8u7
# storage
db|FPGA_DSP_PortLink.(66).cnf
db|FPGA_DSP_PortLink.(66).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_8u7.tdf
3afa6b5b6df3a2a782fe4fbdf1f74caf
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_3v8
# storage
db|FPGA_DSP_PortLink.(67).cnf
db|FPGA_DSP_PortLink.(67).cnf
# case_insensitive
# source_file
db|dffpipe_3v8.tdf
bdf891165762f72d857beb7a8a67f88f
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
add_sub_t5c
# storage
db|FPGA_DSP_PortLink.(68).cnf
db|FPGA_DSP_PortLink.(68).cnf
# case_insensitive
# source_file
db|add_sub_t5c.tdf
7df9dfc190e1a081c06958f8dd486999
6
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# end
# entity
fifo_test
# storage
db|FPGA_DSP_PortLink.(3).cnf
db|FPGA_DSP_PortLink.(3).cnf
# case_insensitive
# source_file
fifo_test.bdf
a1e5169d5c580c14b24d40b8cef0a
23
# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(69).cnf
db|FPGA_DSP_PortLink.(69).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
16
PARAMETER_DEC
USR
LPM_WIDTHU
4
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_9s81
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_9s81
# storage
db|FPGA_DSP_PortLink.(70).cnf
db|FPGA_DSP_PortLink.(70).cnf
# case_insensitive
# source_file
db|dcfifo_9s81.tdf
7e4cce7f10ed24aa5645f815d4f337b
6
# used_port {
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
alt_synch_pipe_9u7
# storage
db|FPGA_DSP_PortLink.(71).cnf
db|FPGA_DSP_PortLink.(71).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_9u7.tdf
94d3aca4e512c56c94b991dec515a45
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_4v8
# storage
db|FPGA_DSP_PortLink.(72).cnf
db|FPGA_DSP_PortLink.(72).cnf
# case_insensitive
# source_file
db|dffpipe_4v8.tdf
f1fc312c9d412c1de6c5646b0f38b58
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_au7
# storage
db|FPGA_DSP_PortLink.(73).cnf
db|FPGA_DSP_PortLink.(73).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_au7.tdf
8d76878d15465751410c0fe8eec645
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_5v8
# storage
db|FPGA_DSP_PortLink.(74).cnf
db|FPGA_DSP_PortLink.(74).cnf
# case_insensitive
# source_file
db|dffpipe_5v8.tdf
ef4d859453c5ab8aadb89184149ee02
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
MUX
# storage
db|FPGA_DSP_PortLink.(2).cnf
db|FPGA_DSP_PortLink.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
MUX.vhd
231cb381fd156919a12f928b3d71fae
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
MUX:inst10
}
# end
# entity
BiPort_Test
# storage
db|FPGA_DSP_PortLink.(1).cnf
db|FPGA_DSP_PortLink.(1).cnf
# case_insensitive
# source_file
BiPort_Test.bdf
c33073b595242a3a22d73faaf1253
23
# end
# entity
lpm_bustri0
# storage
db|FPGA_DSP_PortLink.(31).cnf
db|FPGA_DSP_PortLink.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_bustri0.vhd
9f6e056b82515ddd579134ca3bdac63
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
lpm_bustri
# storage
db|FPGA_DSP_PortLink.(32).cnf
db|FPGA_DSP_PortLink.(32).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|lpm_bustri.tdf
ed9464e1998de88a81948be961c1d04b
6
# user_parameter {
LPM_WIDTH
8
PARAMETER_DEC
USR
}
# used_port {
tridata7
-1
3
tridata6
-1
3
tridata5
-1
3
tridata4
-1
3
tridata3
-1
3
tridata2
-1
3
tridata1
-1
3
tridata0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
enabletr
-1
3
enabledt
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
FIFO_WRN_ByDSP
# storage
db|FPGA_DSP_PortLink.(77).cnf
db|FPGA_DSP_PortLink.(77).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
FIFO_WRN_ByDSP.vhd
8255d3e211303e3b6a1df4d71d398
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}