fpga_dsp_portlink.hif

implemention of FPGA and DSP linking port, using Asynchronous mode

ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_7571
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_7571
# storage
db|FPGA_DSP_PortLink.(34).cnf
db|FPGA_DSP_PortLink.(34).cnf
# case_insensitive
# source_file
db|dcfifo_7571.tdf
219df8ba33376f74aa627bf3b0bae2
6
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
altsyncram_s9r
# storage
db|FPGA_DSP_PortLink.(35).cnf
db|FPGA_DSP_PortLink.(35).cnf
# case_insensitive
# source_file
db|altsyncram_s9r.tdf
b056e2a5c5db62d8872721ca9bd063c6
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b1
-1
3
address_b0
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
alt_synch_pipe_3u7
# storage
db|FPGA_DSP_PortLink.(36).cnf
db|FPGA_DSP_PortLink.(36).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_3u7.tdf
c27aacbd285ecfdc9e4f751a7702d8f
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_tu8
# storage
db|FPGA_DSP_PortLink.(37).cnf
db|FPGA_DSP_PortLink.(37).cnf
# case_insensitive
# source_file
db|dffpipe_tu8.tdf
9b57198492606d18ae0cb80f09b74d5
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_4u7
# storage
db|FPGA_DSP_PortLink.(38).cnf
db|FPGA_DSP_PortLink.(38).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_4u7.tdf
98a95072cf945c677c8f35d9b9757
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_uu8
# storage
db|FPGA_DSP_PortLink.(39).cnf
db|FPGA_DSP_PortLink.(39).cnf
# case_insensitive
# source_file
db|dffpipe_uu8.tdf
a943d656fd38fdaed6c4dec322df0e1
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(40).cnf
db|FPGA_DSP_PortLink.(40).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
4
PARAMETER_DEC
USR
LPM_WIDTHU
2
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_l9a1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrempty
-1
3
wrclk
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdfull
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_l9a1
# storage
db|FPGA_DSP_PortLink.(41).cnf
db|FPGA_DSP_PortLink.(41).cnf
# case_insensitive
# source_file
db|dcfifo_l9a1.tdf
1c2e78e7a9862015112d57787d16bcbc
6
# used_port {
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrempty
-1
3
wrclk
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdfull
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
a_gray2bin_5cb
# storage
db|FPGA_DSP_PortLink.(42).cnf
db|FPGA_DSP_PortLink.(42).cnf
# case_insensitive
# source_file
db|a_gray2bin_5cb.tdf
fb4ea8a42573d26c44a34939216f4f9
6
# used_port {
gray1
-1
3
gray0
-1
3
bin1
-1
3
bin0
-1
3
}
# end
# entity
alt_synch_pipe_297
# storage
db|FPGA_DSP_PortLink.(43).cnf
db|FPGA_DSP_PortLink.(43).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_297.tdf
a13adc48c0f262cc74cddfd91c983c20
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_s98
# storage
db|FPGA_DSP_PortLink.(44).cnf
db|FPGA_DSP_PortLink.(44).cnf
# case_insensitive
# source_file
db|dffpipe_s98.tdf
dce61a1c374e2686913c27bef829ebc
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_qu8
# storage
db|FPGA_DSP_PortLink.(45).cnf
db|FPGA_DSP_PortLink.(45).cnf
# case_insensitive
# source_file
db|dffpipe_qu8.tdf
2c7613821b9163bbf22b5c643cd473
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_5u7
# storage
db|FPGA_DSP_PortLink.(46).cnf
db|FPGA_DSP_PortLink.(46).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_5u7.tdf
bcc59bbaa47d87117ce2f9c0b0c92932
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_vu8
# storage
db|FPGA_DSP_PortLink.(47).cnf
db|FPGA_DSP_PortLink.(47).cnf
# case_insensitive
# source_file
db|dffpipe_vu8.tdf
edef327a65419a85fac4546a3abc5b1
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_397
# storage
db|FPGA_DSP_PortLink.(48).cnf
db|FPGA_DSP_PortLink.(48).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_397.tdf
13a28f2476faae7b65a11450e4ec529
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_t98
# storage
db|FPGA_DSP_PortLink.(49).cnf
db|FPGA_DSP_PortLink.(49).cnf
# case_insensitive
# source_file
db|dffpipe_t98.tdf
378c15157e494f5ac9b7768112d6290
6
# used_port {
q0
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_6u7
# storage
db|FPGA_DSP_PortLink.(50).cnf
db|FPGA_DSP_PortLink.(50).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_6u7.tdf
2285d58a5739e57fadb15839f30cf
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_0v8
# storage
db|FPGA_DSP_PortLink.(51).cnf
db|FPGA_DSP_PortLink.(51).cnf
# case_insensitive
# source_file
db|dffpipe_0v8.tdf
bd4380f3e3fd719bc4965777c73c9fd
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
add_sub_r5c
# storage
db|FPGA_DSP_PortLink.(52).cnf
db|FPGA_DSP_PortLink.(52).cnf
# case_insensitive
# source_file
db|add_sub_r5c.tdf
30c61a62c7bfcddf1a6696c0a1b11777
6
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
}
# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(53).cnf
db|FPGA_DSP_PortLink.(53).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
16
PARAMETER_DEC
USR
LPM_WIDTHU
4
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_aba1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrfull
-1
3
wrempty
-1
3
wrclk
-1
3
rdusedw3
-1
3
rdusedw2
-1
3
rdusedw1
-1
3
rdusedw0
-1
3
rdreq
-1
3
rdfull
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_aba1