fpga_dsp_portlink.hif

implemention of FPGA and DSP linking port, using Asynchronous mode

data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
altsyncram_7e61
# storage
db|FPGA_DSP_PortLink.(15).cnf
db|FPGA_DSP_PortLink.(15).cnf
# case_insensitive
# source_file
db|altsyncram_7e61.tdf
c44bb3fd1a37e610b62b73236a72fe98
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b1
-1
3
address_b0
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
cntr_678
# storage
db|FPGA_DSP_PortLink.(16).cnf
db|FPGA_DSP_PortLink.(16).cnf
# case_insensitive
# source_file
db|cntr_678.tdf
a05207de767b9b6e770f222ce32997
6
# used_port {
sclr
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
cntr_l57
# storage
db|FPGA_DSP_PortLink.(17).cnf
db|FPGA_DSP_PortLink.(17).cnf
# case_insensitive
# source_file
db|cntr_l57.tdf
5e7bb3f6b354fc32f7f6e290ad1e547c
6
# used_port {
updown
-1
3
sclr
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
cntr_778
# storage
db|FPGA_DSP_PortLink.(18).cnf
db|FPGA_DSP_PortLink.(18).cnf
# case_insensitive
# source_file
db|cntr_778.tdf
62a9a3c955e8abd040cbd5862ac1122
6
# used_port {
sclr
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
scfifo
# storage
db|FPGA_DSP_PortLink.(19).cnf
db|FPGA_DSP_PortLink.(19).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|scfifo.tdf
a5f95ef893dfa566cdf5716af337fab4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_DEC
USR
LPM_NUMWORDS
4
PARAMETER_DEC
USR
LPM_WIDTHU
2
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_ccr
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|program files|altera|quartus51|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|program files|altera|quartus51|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
d:|program files|altera|quartus51|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|program files|altera|quartus51|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
}
# end
# entity
scfifo_ccr
# storage
db|FPGA_DSP_PortLink.(20).cnf
db|FPGA_DSP_PortLink.(20).cnf
# case_insensitive
# source_file
db|scfifo_ccr.tdf
64593c3588e56436297df94c62c99cdd
6
# used_port {
wrreq
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
a_dpfifo_jir
# storage
db|FPGA_DSP_PortLink.(21).cnf
db|FPGA_DSP_PortLink.(21).cnf
# case_insensitive
# source_file
db|a_dpfifo_jir.tdf
ca8d3b81a847ff41b4395da37b8a8a3d
6
# used_port {
wreq
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(22).cnf
db|FPGA_DSP_PortLink.(22).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
4
PARAMETER_DEC
USR
LPM_WIDTHU
2
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_5871
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
d:|program files|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
d:|program files|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
d:|program files|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus51|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
d:|program files|altera|quartus51|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
d:|program files|altera|quartus51|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
d:|program files|altera|quartus51|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
d:|program files|altera|quartus51|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
d:|program files|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
d:|program files|altera|quartus51|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_5871
# storage
db|FPGA_DSP_PortLink.(23).cnf
db|FPGA_DSP_PortLink.(23).cnf
# case_insensitive
# source_file
db|dcfifo_5871.tdf
6a3946dcde6abb8e4052c718ec9136
6
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
a_graycounter_986
# storage
db|FPGA_DSP_PortLink.(24).cnf
db|FPGA_DSP_PortLink.(24).cnf
# case_insensitive
# source_file
db|a_graycounter_986.tdf
73145e706fcd77f5366983e8b2c099
6
# used_port {
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
a_graycounter_2j6
# storage
db|FPGA_DSP_PortLink.(25).cnf
db|FPGA_DSP_PortLink.(25).cnf
# case_insensitive
# source_file
db|a_graycounter_2j6.tdf
20c7b2b811cc0f3b819ca24ada44795
6
# used_port {
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
altsyncram_ocr
# storage
db|FPGA_DSP_PortLink.(26).cnf
db|FPGA_DSP_PortLink.(26).cnf
# case_insensitive
# source_file
db|altsyncram_ocr.tdf
a78ce45323b6c7ad38c2e8eae7e6e11
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b1
-1
3
address_b0
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
alt_synch_pipe_1u7
# storage
db|FPGA_DSP_PortLink.(27).cnf
db|FPGA_DSP_PortLink.(27).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_1u7.tdf
bc51872472dcc853d95b1bb6755c17f7
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_ru8
# storage
db|FPGA_DSP_PortLink.(28).cnf
db|FPGA_DSP_PortLink.(28).cnf
# case_insensitive
# source_file
db|dffpipe_ru8.tdf
b9f345e1874a68bc2ce7f72ac6b7a7b
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_2u7
# storage
db|FPGA_DSP_PortLink.(29).cnf
db|FPGA_DSP_PortLink.(29).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_2u7.tdf
2592e97e7e62a312479391048341bbc
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dffpipe_su8
# storage
db|FPGA_DSP_PortLink.(30).cnf
db|FPGA_DSP_PortLink.(30).cnf
# case_insensitive
# source_file
db|dffpipe_su8.tdf
d953ad4f4c31ca84655375a9772c9
6
# used_port {
q1
-1
3
q0
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# end
# entity
dcfifo
# storage
db|FPGA_DSP_PortLink.(33).cnf
db|FPGA_DSP_PortLink.(33).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|dcfifo.tdf
2f14b23f283682a7ddc8d27efed7dbb2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
4
PARAMETER_DEC
USR
LPM_WIDTHU
2
PARAMETER_DEC
USR
LPM_SHOWAHEAD
ON
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING