fpga_dsp_portlink.hif

implemention of FPGA and DSP linking port, using Asynchronous mode

Version 5.1 Build 176 10/26/2005 SJ Full Version
10
724
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
FPGA_DSP_PortLink
# storage
db|FPGA_DSP_PortLink.(0).cnf
db|FPGA_DSP_PortLink.(0).cnf
# case_insensitive
# source_file
FPGA_DSP_PortLink.bdf
a9a0e46fafb5851e4d1a3b2040c1ed39
23
# end
# entity
scfifo
# storage
db|FPGA_DSP_PortLink.(4).cnf
db|FPGA_DSP_PortLink.(4).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|scfifo.tdf
a5f95ef893dfa566cdf5716af337fab4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_DEC
USR
LPM_NUMWORDS
256
PARAMETER_DEC
USR
LPM_WIDTHU
8
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_peq
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|program files|altera|quartus51|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|program files|altera|quartus51|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
d:|program files|altera|quartus51|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|program files|altera|quartus51|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
}
# end
# entity
scfifo_peq
# storage
db|FPGA_DSP_PortLink.(5).cnf
db|FPGA_DSP_PortLink.(5).cnf
# case_insensitive
# source_file
db|scfifo_peq.tdf
a6d9f7b913a9c94e2c1e71d9ccf0614f
6
# used_port {
wrreq
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
a_dpfifo_0lq
# storage
db|FPGA_DSP_PortLink.(6).cnf
db|FPGA_DSP_PortLink.(6).cnf
# case_insensitive
# source_file
db|a_dpfifo_0lq.tdf
b6fc9988ecb5f2dd5ad07559f2fa688
6
# used_port {
wreq
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
altsyncram_5l61
# storage
db|FPGA_DSP_PortLink.(7).cnf
db|FPGA_DSP_PortLink.(7).cnf
# case_insensitive
# source_file
db|altsyncram_5l61.tdf
c1777ccea02eee7f5ce776b22c75e4a
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# end
# entity
altsyncram_rm91
# storage
db|FPGA_DSP_PortLink.(8).cnf
db|FPGA_DSP_PortLink.(8).cnf
# case_insensitive
# source_file
db|altsyncram_rm91.tdf
31598febf8262bf35d7d270796f1275
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
none
0
}
# end
# entity
cntr_c78
# storage
db|FPGA_DSP_PortLink.(9).cnf
db|FPGA_DSP_PortLink.(9).cnf
# case_insensitive
# source_file
db|cntr_c78.tdf
f4ee8febe32c8733359bafa57533c21
6
# used_port {
sclr
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
cntr_r57
# storage
db|FPGA_DSP_PortLink.(10).cnf
db|FPGA_DSP_PortLink.(10).cnf
# case_insensitive
# source_file
db|cntr_r57.tdf
a1f51da348b5d3f075ccaebee71376ca
6
# used_port {
updown
-1
3
sclr
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
cntr_d78
# storage
db|FPGA_DSP_PortLink.(11).cnf
db|FPGA_DSP_PortLink.(11).cnf
# case_insensitive
# source_file
db|cntr_d78.tdf
4965f03281e4e5671736e7ffb8fbd411
6
# used_port {
sclr
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# end
# entity
scfifo
# storage
db|FPGA_DSP_PortLink.(12).cnf
db|FPGA_DSP_PortLink.(12).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus51|libraries|megafunctions|scfifo.tdf
a5f95ef893dfa566cdf5716af337fab4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_DEC
USR
LPM_NUMWORDS
4
PARAMETER_DEC
USR
LPM_WIDTHU
2
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_abq
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
d:|program files|altera|quartus51|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|program files|altera|quartus51|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|program files|altera|quartus51|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
d:|program files|altera|quartus51|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|program files|altera|quartus51|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|program files|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
}
# end
# entity
scfifo_abq
# storage
db|FPGA_DSP_PortLink.(13).cnf
db|FPGA_DSP_PortLink.(13).cnf
# case_insensitive
# source_file
db|scfifo_abq.tdf
5fbd9e927d56d53a4ca21dc8c2adbed0
6
# used_port {
wrreq
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
a_dpfifo_hhq
# storage
db|FPGA_DSP_PortLink.(14).cnf
db|FPGA_DSP_PortLink.(14).cnf
# case_insensitive
# source_file
db|a_dpfifo_hhq.tdf
58efac0ef53c99da2e2e3908d1fcc9d
6
# used_port {
wreq
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3