fpga_dsp_portlink.fit.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C8Q208C7 " "Warning: Timing characteristics of device EP2C8Q208C7 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "16 " "Warning: Found 16 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[15\] 0 " "Warning: Pin \"TO_DSP\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[14\] 0 " "Warning: Pin \"TO_DSP\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[13\] 0 " "Warning: Pin \"TO_DSP\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[12\] 0 " "Warning: Pin \"TO_DSP\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[11\] 0 " "Warning: Pin \"TO_DSP\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[10\] 0 " "Warning: Pin \"TO_DSP\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[9\] 0 " "Warning: Pin \"TO_DSP\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[8\] 0 " "Warning: Pin \"TO_DSP\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[7\] 0 " "Warning: Pin \"TO_DSP\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[6\] 0 " "Warning: Pin \"TO_DSP\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[5\] 0 " "Warning: Pin \"TO_DSP\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[4\] 0 " "Warning: Pin \"TO_DSP\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[3\] 0 " "Warning: Pin \"TO_DSP\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[2\] 0 " "Warning: Pin \"TO_DSP\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[1\] 0 " "Warning: Pin \"TO_DSP\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "TO_DSP\[0\] 0 " "Warning: Pin \"TO_DSP\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "en_blk:inst8\|To_DSP_En~19 " "Info: Following pins have the same output enable: en_blk:inst8\|To_DSP_En~19" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[15\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[15\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[15\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[15] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[14\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[14\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[14\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[14] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[13\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[13\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[13\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[13] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[12\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[12\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[12\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[12] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[11\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[11\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[11\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[11] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[10\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[10\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[10\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[10] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[9\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[9\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[9\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[9] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[8\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[8\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[8\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[8] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[7\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[7\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[7\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[7] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[6\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[6\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[6\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[6] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[5\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[5\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[5\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[5] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[4\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[4\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[4\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[4] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[3\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[3\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[3\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[3] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional TO_DSP\[2\] LVCMOS " "Info: Type bidirectional pin TO_DSP\[2\] uses the LVCMOS I/O standard" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[2\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/