fpga_dsp_portlink.fit.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.492 ns register register " "Info: Estimated most critical path is register to register delay of 7.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|counter_ffa\[0\] 1 REG LAB_X19_Y5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y5; Fanout = 5; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|counter_ffa\[0\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|counter_ffa[0] } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 93 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.422 ns) + CELL(0.178 ns) 1.600 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~79 2 COMB LAB_X22_Y8 1 " "Info: 2: + IC(1.422 ns) + CELL(0.178 ns) = 1.600 ns; Loc. = LAB_X22_Y8; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~79'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.600 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|counter_ffa[0] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.217 ns) + CELL(0.322 ns) 3.139 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~81 3 COMB LAB_X19_Y5 1 " "Info: 3: + IC(1.217 ns) + CELL(0.322 ns) = 3.139 ns; Loc. = LAB_X19_Y5; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~81'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "1.539 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.541 ns) 3.811 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~0 4 COMB LAB_X19_Y5 2 " "Info: 4: + IC(0.131 ns) + CELL(0.541 ns) = 3.811 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|wrfull_eq_comp_aeb_int~0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.672 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 66 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.154 ns) + CELL(0.521 ns) 4.486 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|valid_wrreq 5 COMB LAB_X19_Y5 31 " "Info: 5: + IC(0.154 ns) + CELL(0.521 ns) = 4.486 ns; Loc. = LAB_X19_Y5; Fanout = 31; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|valid_wrreq'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.675 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq } "NODE_NAME" } "" } } { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 74 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.517 ns) 5.478 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|parity~COUT 6 COMB LAB_X19_Y5 2 " "Info: 6: + IC(0.475 ns) + CELL(0.517 ns) = 5.478 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|parity~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.992 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 89 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 5.624 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera0~COUT 7 COMB LAB_X19_Y5 2 " "Info: 7: + IC(0.000 ns) + CELL(0.146 ns) = 5.624 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera0~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 5.770 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera1~COUT 8 COMB LAB_X19_Y5 2 " "Info: 8: + IC(0.000 ns) + CELL(0.146 ns) = 5.770 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera1~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 5.916 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera2~COUT 9 COMB LAB_X19_Y5 2 " "Info: 9: + IC(0.000 ns) + CELL(0.146 ns) = 5.916 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera2~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.062 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera3~COUT 10 COMB LAB_X19_Y5 2 " "Info: 10: + IC(0.000 ns) + CELL(0.146 ns) = 6.062 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera3~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.208 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera4~COUT 11 COMB LAB_X19_Y5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.146 ns) = 6.208 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera4~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 54 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.354 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera5~COUT 12 COMB LAB_X19_Y5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.146 ns) = 6.354 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera5~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 59 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.500 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera6~COUT 13 COMB LAB_X19_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.146 ns) = 6.500 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera6~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 64 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.646 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera7~COUT 14 COMB LAB_X19_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.146 ns) = 6.646 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera7~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 69 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.792 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera8~COUT 15 COMB LAB_X19_Y5 2 " "Info: 15: + IC(0.000 ns) + CELL(0.146 ns) = 6.792 ns; Loc. = LAB_X19_Y5; Fanout = 2; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera8~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 74 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 6.938 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera9~COUT 16 COMB LAB_X19_Y5 1 " "Info: 16: + IC(0.000 ns) + CELL(0.146 ns) = 6.938 ns; Loc. = LAB_X19_Y5; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera9~COUT'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.146 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9~COUT } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 79 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 7.396 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera10 17 COMB LAB_X19_Y5 1 " "Info: 17: + IC(0.000 ns) + CELL(0.458 ns) = 7.396 ns; Loc. = LAB_X19_Y5; Fanout = 1; COMB Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|countera10'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.458 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera10 } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 84 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 7.492 ns FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[10\] 18 REG LAB_X19_Y5 3 " "Info: 18: + IC(0.000 ns) + CELL(0.096 ns) = 7.492 ns; Loc. = LAB_X19_Y5; Fanout = 3; REG Node = 'FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\|power_modified_counter_values\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "0.096 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } } { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 95 31 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.093 ns ( 54.63 % ) " "Info: Total cell delay = 4.093 ns ( 54.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.399 ns ( 45.37 % ) " "Info: Total interconnect delay = 3.399 ns ( 45.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "7.492 ns" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|counter_ffa[0] FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9~COUT FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera10 FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 4 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}