fpga_dsp_portlink.fit.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "en_blk:inst8\|To_DSP_En~19  " "Info: Automatically promoted node en_blk:inst8\|To_DSP_En~19 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[15\] " "Info: Destination node TO_DSP\[15\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[15\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[15] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[15] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[14\] " "Info: Destination node TO_DSP\[14\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[14\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[14] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[14] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[13\] " "Info: Destination node TO_DSP\[13\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[13\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[13] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[13] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[12\] " "Info: Destination node TO_DSP\[12\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[12\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[12] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[12] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[11\] " "Info: Destination node TO_DSP\[11\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[11\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[11] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[11] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[10\] " "Info: Destination node TO_DSP\[10\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[10\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[10] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[10] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[9\] " "Info: Destination node TO_DSP\[9\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[9\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[9] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[9] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[8\] " "Info: Destination node TO_DSP\[8\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[8\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[8] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[8] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[7\] " "Info: Destination node TO_DSP\[7\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[7\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[7] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[7] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TO_DSP\[6\] " "Info: Destination node TO_DSP\[6\]" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 96 1080 1256 112 "TO_DSP\[15..0\]" "" } } } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TO_DSP\[6\]" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { TO_DSP[6] } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { TO_DSP[6] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "en_blk.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/en_blk.vhd" 9 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en_blk:inst8\|To_DSP_En~19" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { en_blk:inst8|To_DSP_En~19 } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { en_blk:inst8|To_DSP_En~19 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdaclr  " "Info: Automatically promoted node FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdaclr " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 54 2 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|rdaclr" } } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_DSP_PortLink" "UNKNOWN" "V1" "E:/ADFM/FPGA_DSP_PortLink/db/FPGA_DSP_PortLink.quartus_db" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/" "" "" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdaclr } "NODE_NAME" } "" } } { "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" { Floorplan "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fld" "" "" { FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdaclr } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}