cntr_snd.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=16 clock q
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_counter 2005:08:24:10:49:38:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.


FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
WITH ( 	LUT_MASK,	SUM_LUTC_INPUT) 
RETURNS ( combout, cout);
FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
RETURNS ( regout);

--synthesis_resources = lut 16 reg 16 
SUBDESIGN cntr_snd
( 
	clock	:	input;
	q[15..0]	:	output;
) 
VARIABLE 
	counter_comb_bita0 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita1 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita2 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita3 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita4 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita5 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita6 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita7 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita8 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita9 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita10 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita11 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita12 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita13 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita14 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita15 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_reg_bit1a[15..0] : cycloneii_lcell_ff;
	aclr_actual	: WIRE;
	clk_en	: NODE;
	cnt_en	: NODE;
	data[15..0]	: NODE;
	external_cin	: WIRE;
	s_val[15..0]	: WIRE;
	safe_q[15..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	sset	: NODE;
	updown_dir	: WIRE;

BEGIN 
	counter_comb_bita[15..0].cin = ( counter_comb_bita[14..0].cout, external_cin);
	counter_comb_bita[15..0].dataa = ( counter_reg_bit1a[15..0].regout);
	counter_comb_bita[15..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
	counter_comb_bita[15..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
	counter_reg_bit1a[].aclr = aclr_actual;
	counter_reg_bit1a[].clk = clock;
	counter_reg_bit1a[].datain = ( counter_comb_bita[15..0].combout);
	counter_reg_bit1a[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
	counter_reg_bit1a[].sdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
	counter_reg_bit1a[].sload = ((sclr # sset) # sload);
	aclr_actual = B"0";
	clk_en = VCC;
	cnt_en = VCC;
	data[] = GND;
	external_cin = B"1";
	q[] = safe_q[];
	s_val[] = B"1111111111111111";
	safe_q[] = counter_reg_bit1a[].regout;
	sclr = GND;
	sload = GND;
	sset = GND;
	updown_dir = B"1";
END;
--VALID FILE