add_sub_k2i.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=2 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


--  Copyright (C) 1991-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = 
SUBDESIGN add_sub_k2i
( 
	cin	:	input;
	dataa[1..0]	:	input;
	datab[1..0]	:	input;
	result[1..0]	:	output;
) 
VARIABLE 
	carry_eqn[1..0]	: WIRE;
	cin_wire	: WIRE;
	datab_node[1..0]	: WIRE;
	sum_eqn[1..0]	: WIRE;

BEGIN 
	carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
	cin_wire = cin;
	datab_node[] = datab[];
	result[] = sum_eqn[];
	sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
END;
--VALID FILE