fpga_dsp_portlink.hier_info

implemention of FPGA and DSP linking port, using Asynchronous mode

address_b[3] => ram_block4a11.PORTBADDR3
address_b[3] => ram_block4a12.PORTBADDR3
address_b[3] => ram_block4a13.PORTBADDR3
address_b[3] => ram_block4a14.PORTBADDR3
address_b[3] => ram_block4a15.PORTBADDR3
address_b[4] => ram_block4a0.PORTBADDR4
address_b[4] => ram_block4a1.PORTBADDR4
address_b[4] => ram_block4a2.PORTBADDR4
address_b[4] => ram_block4a3.PORTBADDR4
address_b[4] => ram_block4a4.PORTBADDR4
address_b[4] => ram_block4a5.PORTBADDR4
address_b[4] => ram_block4a6.PORTBADDR4
address_b[4] => ram_block4a7.PORTBADDR4
address_b[4] => ram_block4a8.PORTBADDR4
address_b[4] => ram_block4a9.PORTBADDR4
address_b[4] => ram_block4a10.PORTBADDR4
address_b[4] => ram_block4a11.PORTBADDR4
address_b[4] => ram_block4a12.PORTBADDR4
address_b[4] => ram_block4a13.PORTBADDR4
address_b[4] => ram_block4a14.PORTBADDR4
address_b[4] => ram_block4a15.PORTBADDR4
address_b[5] => ram_block4a0.PORTBADDR5
address_b[5] => ram_block4a1.PORTBADDR5
address_b[5] => ram_block4a2.PORTBADDR5
address_b[5] => ram_block4a3.PORTBADDR5
address_b[5] => ram_block4a4.PORTBADDR5
address_b[5] => ram_block4a5.PORTBADDR5
address_b[5] => ram_block4a6.PORTBADDR5
address_b[5] => ram_block4a7.PORTBADDR5
address_b[5] => ram_block4a8.PORTBADDR5
address_b[5] => ram_block4a9.PORTBADDR5
address_b[5] => ram_block4a10.PORTBADDR5
address_b[5] => ram_block4a11.PORTBADDR5
address_b[5] => ram_block4a12.PORTBADDR5
address_b[5] => ram_block4a13.PORTBADDR5
address_b[5] => ram_block4a14.PORTBADDR5
address_b[5] => ram_block4a15.PORTBADDR5
address_b[6] => ram_block4a0.PORTBADDR6
address_b[6] => ram_block4a1.PORTBADDR6
address_b[6] => ram_block4a2.PORTBADDR6
address_b[6] => ram_block4a3.PORTBADDR6
address_b[6] => ram_block4a4.PORTBADDR6
address_b[6] => ram_block4a5.PORTBADDR6
address_b[6] => ram_block4a6.PORTBADDR6
address_b[6] => ram_block4a7.PORTBADDR6
address_b[6] => ram_block4a8.PORTBADDR6
address_b[6] => ram_block4a9.PORTBADDR6
address_b[6] => ram_block4a10.PORTBADDR6
address_b[6] => ram_block4a11.PORTBADDR6
address_b[6] => ram_block4a12.PORTBADDR6
address_b[6] => ram_block4a13.PORTBADDR6
address_b[6] => ram_block4a14.PORTBADDR6
address_b[6] => ram_block4a15.PORTBADDR6
address_b[7] => ram_block4a0.PORTBADDR7
address_b[7] => ram_block4a1.PORTBADDR7
address_b[7] => ram_block4a2.PORTBADDR7
address_b[7] => ram_block4a3.PORTBADDR7
address_b[7] => ram_block4a4.PORTBADDR7
address_b[7] => ram_block4a5.PORTBADDR7
address_b[7] => ram_block4a6.PORTBADDR7
address_b[7] => ram_block4a7.PORTBADDR7
address_b[7] => ram_block4a8.PORTBADDR7
address_b[7] => ram_block4a9.PORTBADDR7
address_b[7] => ram_block4a10.PORTBADDR7
address_b[7] => ram_block4a11.PORTBADDR7
address_b[7] => ram_block4a12.PORTBADDR7
address_b[7] => ram_block4a13.PORTBADDR7
address_b[7] => ram_block4a14.PORTBADDR7
address_b[7] => ram_block4a15.PORTBADDR7
address_b[8] => ram_block4a0.PORTBADDR8
address_b[8] => ram_block4a1.PORTBADDR8
address_b[8] => ram_block4a2.PORTBADDR8
address_b[8] => ram_block4a3.PORTBADDR8
address_b[8] => ram_block4a4.PORTBADDR8
address_b[8] => ram_block4a5.PORTBADDR8
address_b[8] => ram_block4a6.PORTBADDR8
address_b[8] => ram_block4a7.PORTBADDR8
address_b[8] => ram_block4a8.PORTBADDR8
address_b[8] => ram_block4a9.PORTBADDR8
address_b[8] => ram_block4a10.PORTBADDR8
address_b[8] => ram_block4a11.PORTBADDR8
address_b[8] => ram_block4a12.PORTBADDR8
address_b[8] => ram_block4a13.PORTBADDR8
address_b[8] => ram_block4a14.PORTBADDR8
address_b[8] => ram_block4a15.PORTBADDR8
address_b[9] => ram_block4a0.PORTBADDR9
address_b[9] => ram_block4a1.PORTBADDR9
address_b[9] => ram_block4a2.PORTBADDR9
address_b[9] => ram_block4a3.PORTBADDR9
address_b[9] => ram_block4a4.PORTBADDR9
address_b[9] => ram_block4a5.PORTBADDR9
address_b[9] => ram_block4a6.PORTBADDR9
address_b[9] => ram_block4a7.PORTBADDR9
address_b[9] => ram_block4a8.PORTBADDR9
address_b[9] => ram_block4a9.PORTBADDR9
address_b[9] => ram_block4a10.PORTBADDR9
address_b[9] => ram_block4a11.PORTBADDR9
address_b[9] => ram_block4a12.PORTBADDR9
address_b[9] => ram_block4a13.PORTBADDR9
address_b[9] => ram_block4a14.PORTBADDR9
address_b[9] => ram_block4a15.PORTBADDR9
address_b[10] => ram_block4a0.PORTBADDR10
address_b[10] => ram_block4a1.PORTBADDR10
address_b[10] => ram_block4a2.PORTBADDR10
address_b[10] => ram_block4a3.PORTBADDR10
address_b[10] => ram_block4a4.PORTBADDR10
address_b[10] => ram_block4a5.PORTBADDR10
address_b[10] => ram_block4a6.PORTBADDR10
address_b[10] => ram_block4a7.PORTBADDR10
address_b[10] => ram_block4a8.PORTBADDR10
address_b[10] => ram_block4a9.PORTBADDR10
address_b[10] => ram_block4a10.PORTBADDR10
address_b[10] => ram_block4a11.PORTBADDR10
address_b[10] => ram_block4a12.PORTBADDR10
address_b[10] => ram_block4a13.PORTBADDR10
address_b[10] => ram_block4a14.PORTBADDR10
address_b[10] => ram_block4a15.PORTBADDR10
addressstall_a => ram_block4a0.PORTAADDRSTALL
addressstall_a => ram_block4a1.PORTAADDRSTALL
addressstall_a => ram_block4a2.PORTAADDRSTALL
addressstall_a => ram_block4a3.PORTAADDRSTALL
addressstall_a => ram_block4a4.PORTAADDRSTALL
addressstall_a => ram_block4a5.PORTAADDRSTALL
addressstall_a => ram_block4a6.PORTAADDRSTALL
addressstall_a => ram_block4a7.PORTAADDRSTALL
addressstall_a => ram_block4a8.PORTAADDRSTALL
addressstall_a => ram_block4a9.PORTAADDRSTALL
addressstall_a => ram_block4a10.PORTAADDRSTALL
addressstall_a => ram_block4a11.PORTAADDRSTALL
addressstall_a => ram_block4a12.PORTAADDRSTALL
addressstall_a => ram_block4a13.PORTAADDRSTALL
addressstall_a => ram_block4a14.PORTAADDRSTALL
addressstall_a => ram_block4a15.PORTAADDRSTALL
clock0 => ram_block4a0.CLK0
clock0 => ram_block4a1.CLK0
clock0 => ram_block4a2.CLK0
clock0 => ram_block4a3.CLK0
clock0 => ram_block4a4.CLK0
clock0 => ram_block4a5.CLK0
clock0 => ram_block4a6.CLK0
clock0 => ram_block4a7.CLK0
clock0 => ram_block4a8.CLK0
clock0 => ram_block4a9.CLK0
clock0 => ram_block4a10.CLK0
clock0 => ram_block4a11.CLK0
clock0 => ram_block4a12.CLK0
clock0 => ram_block4a13.CLK0
clock0 => ram_block4a14.CLK0
clock0 => ram_block4a15.CLK0
clock1 => ram_block4a0.CLK1
clock1 => ram_block4a1.CLK1
clock1 => ram_block4a2.CLK1
clock1 => ram_block4a3.CLK1
clock1 => ram_block4a4.CLK1
clock1 => ram_block4a5.CLK1
clock1 => ram_block4a6.CLK1
clock1 => ram_block4a7.CLK1
clock1 => ram_block4a8.CLK1
clock1 => ram_block4a9.CLK1
clock1 => ram_block4a10.CLK1
clock1 => ram_block4a11.CLK1
clock1 => ram_block4a12.CLK1
clock1 => ram_block4a13.CLK1
clock1 => ram_block4a14.CLK1
clock1 => ram_block4a15.CLK1
clocken0 => ram_block4a0.ENA0
clocken0 => ram_block4a1.ENA0
clocken0 => ram_block4a2.ENA0
clocken0 => ram_block4a3.ENA0
clocken0 => ram_block4a4.ENA0
clocken0 => ram_block4a5.ENA0
clocken0 => ram_block4a6.ENA0
clocken0 => ram_block4a7.ENA0
clocken0 => ram_block4a8.ENA0
clocken0 => ram_block4a9.ENA0
clocken0 => ram_block4a10.ENA0
clocken0 => ram_block4a11.ENA0
clocken0 => ram_block4a12.ENA0
clocken0 => ram_block4a13.ENA0
clocken0 => ram_block4a14.ENA0
clocken0 => ram_block4a15.ENA0
data_a[0] => ram_block4a0.PORTADATAIN
data_a[1] => ram_block4a1.PORTADATAIN
data_a[2] => ram_block4a2.PORTADATAIN
data_a[3] => ram_block4a3.PORTADATAIN
data_a[4] => ram_block4a4.PORTADATAIN
data_a[5] => ram_block4a5.PORTADATAIN
data_a[6] => ram_block4a6.PORTADATAIN
data_a[7] => ram_block4a7.PORTADATAIN
data_a[8] => ram_block4a8.PORTADATAIN
data_a[9] => ram_block4a9.PORTADATAIN
data_a[10] => ram_block4a10.PORTADATAIN
data_a[11] => ram_block4a11.PORTADATAIN
data_a[12] => ram_block4a12.PORTADATAIN
data_a[13] => ram_block4a13.PORTADATAIN
data_a[14] => ram_block4a14.PORTADATAIN
data_a[15] => ram_block4a15.PORTADATAIN
data_b[0] => ram_block4a0.PORTBDATAIN
data_b[1] => ram_block4a1.PORTBDATAIN
data_b[2] => ram_block4a2.PORTBDATAIN
data_b[3] => ram_block4a3.PORTBDATAIN
data_b[4] => ram_block4a4.PORTBDATAIN
data_b[5] => ram_block4a5.PORTBDATAIN
data_b[6] => ram_block4a6.PORTBDATAIN
data_b[7] => ram_block4a7.PORTBDATAIN
data_b[8] => ram_block4a8.PORTBDATAIN
data_b[9] => ram_block4a9.PORTBDATAIN
data_b[10] => ram_block4a10.PORTBDATAIN
data_b[11] => ram_block4a11.PORTBDATAIN
data_b[12] => ram_block4a12.PORTBDATAIN
data_b[13] => ram_block4a13.PORTBDATAIN
data_b[14] => ram_block4a14.PORTBDATAIN
data_b[15] => ram_block4a15.PORTBDATAIN
q_a[0] <= ram_block4a0.PORTADATAOUT
q_a[1] <= ram_block4a1.PORTADATAOUT
q_a[2] <= ram_block4a2.PORTADATAOUT
q_a[3] <= ram_block4a3.PORTADATAOUT
q_a[4] <= ram_block4a4.PORTADATAOUT
q_a[5] <= ram_block4a5.PORTADATAOUT
q_a[6] <= ram_block4a6.PORTADATAOUT
q_a[7] <= ram_block4a7.PORTADATAOUT
q_a[8] <= ram_block4a8.PORTADATAOUT
q_a[9] <= ram_block4a9.PORTADATAOUT
q_a[10] <= ram_block4a10.PORTADATAOUT
q_a[11] <= ram_block4a11.PORTADATAOUT
q_a[12] <= ram_block4a12.PORTADATAOUT
q_a[13] <= ram_block4a13.PORTADATAOUT
q_a[14] <= ram_block4a14.PORTADATAOUT
q_a[15] <= ram_block4a15.PORTADATAOUT
q_b[0] <= ram_block4a0.PORTBDATAOUT
q_b[1] <= ram_block4a1.PORTBDATAOUT
q_b[2] <= ram_block4a2.PORTBDATAOUT
q_b[3] <= ram_block4a3.PORTBDATAOUT
q_b[4] <= ram_block4a4.PORTBDATAOUT
q_b[5] <= ram_block4a5.PORTBDATAOUT
q_b[6] <= ram_block4a6.PORTBDATAOUT
q_b[7] <= ram_block4a7.PORTBDATAOUT
q_b[8] <= ram_block4a8.PORTBDATAOUT
q_b[9] <= ram_block4a9.PORTBDATAOUT
q_b[10] <= ram_block4a10.PORTBDATAOUT
q_b[11] <= ram_block4a11.PORTBDATAOUT
q_b[12] <= ram_block4a12.PORTBDATAOUT
q_b[13] <= ram_block4a13.PORTBDATAOUT
q_b[14] <= ram_block4a14.PORTBDATAOUT
q_b[15] <= ram_block4a15.PORTBDATAOUT
wren_a => ram_block4a0.PORTAWE
wren_a => ram_block4a1.PORTAWE
wren_a => ram_block4a2.PORTAWE
wren_a => ram_block4a3.PORTAWE
wren_a => ram_block4a4.PORTAWE
wren_a => ram_block4a5.PORTAWE
wren_a => ram_block4a6.PORTAWE
wren_a => ram_block4a7.PORTAWE
wren_a => ram_block4a8.PORTAWE
wren_a => ram_block4a9.PORTAWE
wren_a => ram_block4a10.PORTAWE
wren_a => ram_block4a11.PORTAWE
wren_a => ram_block4a12.PORTAWE
wren_a => ram_block4a13.PORTAWE
wren_a => ram_block4a14.PORTAWE
wren_a => ram_block4a15.PORTAWE
wren_b => ram_block4a0.PORTBRE
wren_b => ram_block4a1.PORTBRE
wren_b => ram_block4a2.PORTBRE
wren_b => ram_block4a3.PORTBRE
wren_b => ram_block4a4.PORTBRE
wren_b => ram_block4a5.PORTBRE
wren_b => ram_block4a6.PORTBRE
wren_b => ram_block4a7.PORTBRE
wren_b => ram_block4a8.PORTBRE
wren_b => ram_block4a9.PORTBRE
wren_b => ram_block4a10.PORTBRE
wren_b => ram_block4a11.PORTBRE
wren_b => ram_block4a12.PORTBRE
wren_b => ram_block4a13.PORTBRE
wren_b => ram_block4a14.PORTBRE
wren_b => ram_block4a15.PORTBRE


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp
clock => dffpipe_b09:dffpipe5.clock
d[0] => dffpipe_b09:dffpipe5.d[0]
d[1] => dffpipe_b09:dffpipe5.d[1]
d[2] => dffpipe_b09:dffpipe5.d[2]
d[3] => dffpipe_b09:dffpipe5.d[3]
d[4] => dffpipe_b09:dffpipe5.d[4]
d[5] => dffpipe_b09:dffpipe5.d[5]
d[6] => dffpipe_b09:dffpipe5.d[6]
d[7] => dffpipe_b09:dffpipe5.d[7]
d[8] => dffpipe_b09:dffpipe5.d[8]
d[9] => dffpipe_b09:dffpipe5.d[9]
d[10] => dffpipe_b09:dffpipe5.d[10]
q[0] <= dffpipe_b09:dffpipe5.q[0]
q[1] <= dffpipe_b09:dffpipe5.q[1]
q[2] <= dffpipe_b09:dffpipe5.q[2]
q[3] <= dffpipe_b09:dffpipe5.q[3]
q[4] <= dffpipe_b09:dffpipe5.q[4]
q[5] <= dffpipe_b09:dffpipe5.q[5]
q[6] <= dffpipe_b09:dffpipe5.q[6]
q[7] <= dffpipe_b09:dffpipe5.q[7]
q[8] <= dffpipe_b09:dffpipe5.q[8]
q[9] <= dffpipe_b09:dffpipe5.q[9]
q[10] <= dffpipe_b09:dffpipe5.q[10]


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5
clock => dffe6a[10].CLK
clock => dffe6a[9].CLK
clock => dffe6a[8].CLK
clock => dffe6a[7].CLK
clock => dffe6a[6].CLK
clock => dffe6a[5].CLK
clock => dffe6a[4].CLK
clock => dffe6a[3].CLK
clock => dffe6a[2].CLK
clock => dffe6a[1].CLK
clock => dffe6a[0].CLK
clock => dffe7a[10].CLK
clock => dffe7a[9].CLK
clock => dffe7a[8].CLK
clock => dffe7a[7].CLK
clock => dffe7a[6].CLK
clock => dffe7a[5].CLK
clock => dffe7a[4].CLK
clock => dffe7a[3].CLK
clock => dffe7a[2].CLK
clock => dffe7a[1].CLK
clock => dffe7a[0].CLK
q[0] <= dffe7a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe7a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe7a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe7a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe7a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe7a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe7a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe7a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe7a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe7a[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffe7a[10].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp
clock => dffpipe_c09:dffpipe8.clock
d[0] => dffpipe_c09:dffpipe8.d[0]
d[1] => dffpipe_c09:dffpipe8.d[1]
d[2] => dffpipe_c09:dffpipe8.d[2]
d[3] => dffpipe_c09:dffpipe8.d[3]
d[4] => dffpipe_c09:dffpipe8.d[4]
d[5] => dffpipe_c09:dffpipe8.d[5]
d[6] => dffpipe_c09:dffpipe8.d[6]
d[7] => dffpipe_c09:dffpipe8.d[7]
d[8] => dffpipe_c09:dffpipe8.d[8]
d[9] => dffpipe_c09:dffpipe8.d[9]
d[10] => dffpipe_c09:dffpipe8.d[10]
q[0] <= dffpipe_c09:dffpipe8.q[0]
q[1] <= dffpipe_c09:dffpipe8.q[1]
q[2] <= dffpipe_c09:dffpipe8.q[2]
q[3] <= dffpipe_c09:dffpipe8.q[3]
q[4] <= dffpipe_c09:dffpipe8.q[4]
q[5] <= dffpipe_c09:dffpipe8.q[5]
q[6] <= dffpipe_c09:dffpipe8.q[6]
q[7] <= dffpipe_c09:dffpipe8.q[7]
q[8] <= dffpipe_c09:dffpipe8.q[8]
q[9] <= dffpipe_c09:dffpipe8.q[9]
q[10] <= dffpipe_c09:dffpipe8.q[10]


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8
clock => dffe10a[10].CLK
clock => dffe10a[9].CLK
clock => dffe10a[8].CLK
clock => dffe10a[7].CLK
clock => dffe10a[6].CLK
clock => dffe10a[5].CLK
clock => dffe10a[4].CLK
clock => dffe10a[3].CLK
clock => dffe10a[2].CLK
clock => dffe10a[1].CLK
clock => dffe10a[0].CLK
clock => dffe9a[10].CLK
clock => dffe9a[9].CLK
clock => dffe9a[8].CLK
clock => dffe9a[7].CLK
clock => dffe9a[6].CLK
clock => dffe9a[5].CLK
clock => dffe9a[4].CLK
clock => dffe9a[3].CLK
clock => dffe9a[2].CLK
clock => dffe9a[1].CLK
clock => dffe9a[0].CLK
q[0] <= dffe10a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe10a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe10a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe10a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe10a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe10a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe10a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe10a[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffe10a[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffe10a[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffe10a[10].DB_MAX_OUTPUT_PORT_TYPE