fpga_dsp_portlink.hier_info

implemention of FPGA and DSP linking port, using Asynchronous mode

rdclk => rdptr_g[7].CLK
rdclk => rdptr_g[6].CLK
rdclk => rdptr_g[5].CLK
rdclk => rdptr_g[4].CLK
rdclk => rdptr_g[3].CLK
rdclk => rdptr_g[2].CLK
rdclk => rdptr_g[1].CLK
rdclk => rdptr_g[0].CLK
rdempty <= rdempty_eq_comp_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
rdreq => valid_rdreq.IN0
wrclk => a_graycounter_ik6:wrptr_g1p.clock
wrclk => altsyncram_ofr:fifo_ram.clock0
wrclk => alt_synch_pipe_iv7:ws_dgrp.clock
wrclk => delayed_wrptr_g[10].CLK
wrclk => delayed_wrptr_g[9].CLK
wrclk => delayed_wrptr_g[8].CLK
wrclk => delayed_wrptr_g[7].CLK
wrclk => delayed_wrptr_g[6].CLK
wrclk => delayed_wrptr_g[5].CLK
wrclk => delayed_wrptr_g[4].CLK
wrclk => delayed_wrptr_g[3].CLK
wrclk => delayed_wrptr_g[2].CLK
wrclk => delayed_wrptr_g[1].CLK
wrclk => delayed_wrptr_g[0].CLK
wrclk => wrptr_g[10].CLK
wrclk => wrptr_g[9].CLK
wrclk => wrptr_g[8].CLK
wrclk => wrptr_g[7].CLK
wrclk => wrptr_g[6].CLK
wrclk => wrptr_g[5].CLK
wrclk => wrptr_g[4].CLK
wrclk => wrptr_g[3].CLK
wrclk => wrptr_g[2].CLK
wrclk => wrptr_g[1].CLK
wrclk => wrptr_g[0].CLK
wrfull <= wrfull_eq_comp_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
wrreq => valid_wrreq.IN0


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p
aclr => counter_ffa[10].ACLR
aclr => counter_ffa[9].ACLR
aclr => counter_ffa[8].ACLR
aclr => counter_ffa[7].ACLR
aclr => counter_ffa[6].ACLR
aclr => counter_ffa[5].ACLR
aclr => counter_ffa[4].ACLR
aclr => counter_ffa[3].ACLR
aclr => counter_ffa[2].ACLR
aclr => counter_ffa[1].ACLR
aclr => counter_ffa[0].ACLR
aclr => parity_ff.ACLR
clock => counter_ffa[10].CLK
clock => counter_ffa[9].CLK
clock => counter_ffa[8].CLK
clock => counter_ffa[7].CLK
clock => counter_ffa[6].CLK
clock => counter_ffa[5].CLK
clock => counter_ffa[4].CLK
clock => counter_ffa[3].CLK
clock => counter_ffa[2].CLK
clock => counter_ffa[1].CLK
clock => counter_ffa[0].CLK
clock => parity_ff.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= counter_ffa[0].REGOUT
q[1] <= counter_ffa[1].REGOUT
q[2] <= counter_ffa[2].REGOUT
q[3] <= counter_ffa[3].REGOUT
q[4] <= counter_ffa[4].REGOUT
q[5] <= counter_ffa[5].REGOUT
q[6] <= counter_ffa[6].REGOUT
q[7] <= counter_ffa[7].REGOUT
q[8] <= counter_ffa[8].REGOUT
q[9] <= counter_ffa[9].REGOUT
q[10] <= counter_ffa[10].REGOUT


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p
clock => counter_ffa[10].CLK
clock => counter_ffa[9].CLK
clock => counter_ffa[8].CLK
clock => counter_ffa[7].CLK
clock => counter_ffa[6].CLK
clock => counter_ffa[5].CLK
clock => counter_ffa[4].CLK
clock => counter_ffa[3].CLK
clock => counter_ffa[2].CLK
clock => counter_ffa[1].CLK
clock => counter_ffa[0].CLK
clock => parity_ff.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= power_modified_counter_values[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= counter_ffa[1].REGOUT
q[2] <= counter_ffa[2].REGOUT
q[3] <= counter_ffa[3].REGOUT
q[4] <= counter_ffa[4].REGOUT
q[5] <= counter_ffa[5].REGOUT
q[6] <= counter_ffa[6].REGOUT
q[7] <= counter_ffa[7].REGOUT
q[8] <= counter_ffa[8].REGOUT
q[9] <= counter_ffa[9].REGOUT
q[10] <= counter_ffa[10].REGOUT


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram
address_a[0] => altsyncram_uk61:altsyncram3.address_b[0]
address_a[1] => altsyncram_uk61:altsyncram3.address_b[1]
address_a[2] => altsyncram_uk61:altsyncram3.address_b[2]
address_a[3] => altsyncram_uk61:altsyncram3.address_b[3]
address_a[4] => altsyncram_uk61:altsyncram3.address_b[4]
address_a[5] => altsyncram_uk61:altsyncram3.address_b[5]
address_a[6] => altsyncram_uk61:altsyncram3.address_b[6]
address_a[7] => altsyncram_uk61:altsyncram3.address_b[7]
address_a[8] => altsyncram_uk61:altsyncram3.address_b[8]
address_a[9] => altsyncram_uk61:altsyncram3.address_b[9]
address_a[10] => altsyncram_uk61:altsyncram3.address_b[10]
address_b[0] => altsyncram_uk61:altsyncram3.address_a[0]
address_b[1] => altsyncram_uk61:altsyncram3.address_a[1]
address_b[2] => altsyncram_uk61:altsyncram3.address_a[2]
address_b[3] => altsyncram_uk61:altsyncram3.address_a[3]
address_b[4] => altsyncram_uk61:altsyncram3.address_a[4]
address_b[5] => altsyncram_uk61:altsyncram3.address_a[5]
address_b[6] => altsyncram_uk61:altsyncram3.address_a[6]
address_b[7] => altsyncram_uk61:altsyncram3.address_a[7]
address_b[8] => altsyncram_uk61:altsyncram3.address_a[8]
address_b[9] => altsyncram_uk61:altsyncram3.address_a[9]
address_b[10] => altsyncram_uk61:altsyncram3.address_a[10]
addressstall_b => altsyncram_uk61:altsyncram3.addressstall_a
clock0 => altsyncram_uk61:altsyncram3.clock1
clock1 => altsyncram_uk61:altsyncram3.clock0
clocken1 => altsyncram_uk61:altsyncram3.clocken0
data_a[0] => altsyncram_uk61:altsyncram3.data_b[0]
data_a[1] => altsyncram_uk61:altsyncram3.data_b[1]
data_a[2] => altsyncram_uk61:altsyncram3.data_b[2]
data_a[3] => altsyncram_uk61:altsyncram3.data_b[3]
data_a[4] => altsyncram_uk61:altsyncram3.data_b[4]
data_a[5] => altsyncram_uk61:altsyncram3.data_b[5]
data_a[6] => altsyncram_uk61:altsyncram3.data_b[6]
data_a[7] => altsyncram_uk61:altsyncram3.data_b[7]
data_a[8] => altsyncram_uk61:altsyncram3.data_b[8]
data_a[9] => altsyncram_uk61:altsyncram3.data_b[9]
data_a[10] => altsyncram_uk61:altsyncram3.data_b[10]
data_a[11] => altsyncram_uk61:altsyncram3.data_b[11]
data_a[12] => altsyncram_uk61:altsyncram3.data_b[12]
data_a[13] => altsyncram_uk61:altsyncram3.data_b[13]
data_a[14] => altsyncram_uk61:altsyncram3.data_b[14]
data_a[15] => altsyncram_uk61:altsyncram3.data_b[15]
q_b[0] <= altsyncram_uk61:altsyncram3.q_a[0]
q_b[1] <= altsyncram_uk61:altsyncram3.q_a[1]
q_b[2] <= altsyncram_uk61:altsyncram3.q_a[2]
q_b[3] <= altsyncram_uk61:altsyncram3.q_a[3]
q_b[4] <= altsyncram_uk61:altsyncram3.q_a[4]
q_b[5] <= altsyncram_uk61:altsyncram3.q_a[5]
q_b[6] <= altsyncram_uk61:altsyncram3.q_a[6]
q_b[7] <= altsyncram_uk61:altsyncram3.q_a[7]
q_b[8] <= altsyncram_uk61:altsyncram3.q_a[8]
q_b[9] <= altsyncram_uk61:altsyncram3.q_a[9]
q_b[10] <= altsyncram_uk61:altsyncram3.q_a[10]
q_b[11] <= altsyncram_uk61:altsyncram3.q_a[11]
q_b[12] <= altsyncram_uk61:altsyncram3.q_a[12]
q_b[13] <= altsyncram_uk61:altsyncram3.q_a[13]
q_b[14] <= altsyncram_uk61:altsyncram3.q_a[14]
q_b[15] <= altsyncram_uk61:altsyncram3.q_a[15]
wren_a => altsyncram_uk61:altsyncram3.wren_b


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3
address_a[0] => ram_block4a0.PORTAADDR
address_a[0] => ram_block4a1.PORTAADDR
address_a[0] => ram_block4a2.PORTAADDR
address_a[0] => ram_block4a3.PORTAADDR
address_a[0] => ram_block4a4.PORTAADDR
address_a[0] => ram_block4a5.PORTAADDR
address_a[0] => ram_block4a6.PORTAADDR
address_a[0] => ram_block4a7.PORTAADDR
address_a[0] => ram_block4a8.PORTAADDR
address_a[0] => ram_block4a9.PORTAADDR
address_a[0] => ram_block4a10.PORTAADDR
address_a[0] => ram_block4a11.PORTAADDR
address_a[0] => ram_block4a12.PORTAADDR
address_a[0] => ram_block4a13.PORTAADDR
address_a[0] => ram_block4a14.PORTAADDR
address_a[0] => ram_block4a15.PORTAADDR
address_a[1] => ram_block4a0.PORTAADDR1
address_a[1] => ram_block4a1.PORTAADDR1
address_a[1] => ram_block4a2.PORTAADDR1
address_a[1] => ram_block4a3.PORTAADDR1
address_a[1] => ram_block4a4.PORTAADDR1
address_a[1] => ram_block4a5.PORTAADDR1
address_a[1] => ram_block4a6.PORTAADDR1
address_a[1] => ram_block4a7.PORTAADDR1
address_a[1] => ram_block4a8.PORTAADDR1
address_a[1] => ram_block4a9.PORTAADDR1
address_a[1] => ram_block4a10.PORTAADDR1
address_a[1] => ram_block4a11.PORTAADDR1
address_a[1] => ram_block4a12.PORTAADDR1
address_a[1] => ram_block4a13.PORTAADDR1
address_a[1] => ram_block4a14.PORTAADDR1
address_a[1] => ram_block4a15.PORTAADDR1
address_a[2] => ram_block4a0.PORTAADDR2
address_a[2] => ram_block4a1.PORTAADDR2
address_a[2] => ram_block4a2.PORTAADDR2
address_a[2] => ram_block4a3.PORTAADDR2
address_a[2] => ram_block4a4.PORTAADDR2
address_a[2] => ram_block4a5.PORTAADDR2
address_a[2] => ram_block4a6.PORTAADDR2
address_a[2] => ram_block4a7.PORTAADDR2
address_a[2] => ram_block4a8.PORTAADDR2
address_a[2] => ram_block4a9.PORTAADDR2
address_a[2] => ram_block4a10.PORTAADDR2
address_a[2] => ram_block4a11.PORTAADDR2
address_a[2] => ram_block4a12.PORTAADDR2
address_a[2] => ram_block4a13.PORTAADDR2
address_a[2] => ram_block4a14.PORTAADDR2
address_a[2] => ram_block4a15.PORTAADDR2
address_a[3] => ram_block4a0.PORTAADDR3
address_a[3] => ram_block4a1.PORTAADDR3
address_a[3] => ram_block4a2.PORTAADDR3
address_a[3] => ram_block4a3.PORTAADDR3
address_a[3] => ram_block4a4.PORTAADDR3
address_a[3] => ram_block4a5.PORTAADDR3
address_a[3] => ram_block4a6.PORTAADDR3
address_a[3] => ram_block4a7.PORTAADDR3
address_a[3] => ram_block4a8.PORTAADDR3
address_a[3] => ram_block4a9.PORTAADDR3
address_a[3] => ram_block4a10.PORTAADDR3
address_a[3] => ram_block4a11.PORTAADDR3
address_a[3] => ram_block4a12.PORTAADDR3
address_a[3] => ram_block4a13.PORTAADDR3
address_a[3] => ram_block4a14.PORTAADDR3
address_a[3] => ram_block4a15.PORTAADDR3
address_a[4] => ram_block4a0.PORTAADDR4
address_a[4] => ram_block4a1.PORTAADDR4
address_a[4] => ram_block4a2.PORTAADDR4
address_a[4] => ram_block4a3.PORTAADDR4
address_a[4] => ram_block4a4.PORTAADDR4
address_a[4] => ram_block4a5.PORTAADDR4
address_a[4] => ram_block4a6.PORTAADDR4
address_a[4] => ram_block4a7.PORTAADDR4
address_a[4] => ram_block4a8.PORTAADDR4
address_a[4] => ram_block4a9.PORTAADDR4
address_a[4] => ram_block4a10.PORTAADDR4
address_a[4] => ram_block4a11.PORTAADDR4
address_a[4] => ram_block4a12.PORTAADDR4
address_a[4] => ram_block4a13.PORTAADDR4
address_a[4] => ram_block4a14.PORTAADDR4
address_a[4] => ram_block4a15.PORTAADDR4
address_a[5] => ram_block4a0.PORTAADDR5
address_a[5] => ram_block4a1.PORTAADDR5
address_a[5] => ram_block4a2.PORTAADDR5
address_a[5] => ram_block4a3.PORTAADDR5
address_a[5] => ram_block4a4.PORTAADDR5
address_a[5] => ram_block4a5.PORTAADDR5
address_a[5] => ram_block4a6.PORTAADDR5
address_a[5] => ram_block4a7.PORTAADDR5
address_a[5] => ram_block4a8.PORTAADDR5
address_a[5] => ram_block4a9.PORTAADDR5
address_a[5] => ram_block4a10.PORTAADDR5
address_a[5] => ram_block4a11.PORTAADDR5
address_a[5] => ram_block4a12.PORTAADDR5
address_a[5] => ram_block4a13.PORTAADDR5
address_a[5] => ram_block4a14.PORTAADDR5
address_a[5] => ram_block4a15.PORTAADDR5
address_a[6] => ram_block4a0.PORTAADDR6
address_a[6] => ram_block4a1.PORTAADDR6
address_a[6] => ram_block4a2.PORTAADDR6
address_a[6] => ram_block4a3.PORTAADDR6
address_a[6] => ram_block4a4.PORTAADDR6
address_a[6] => ram_block4a5.PORTAADDR6
address_a[6] => ram_block4a6.PORTAADDR6
address_a[6] => ram_block4a7.PORTAADDR6
address_a[6] => ram_block4a8.PORTAADDR6
address_a[6] => ram_block4a9.PORTAADDR6
address_a[6] => ram_block4a10.PORTAADDR6
address_a[6] => ram_block4a11.PORTAADDR6
address_a[6] => ram_block4a12.PORTAADDR6
address_a[6] => ram_block4a13.PORTAADDR6
address_a[6] => ram_block4a14.PORTAADDR6
address_a[6] => ram_block4a15.PORTAADDR6
address_a[7] => ram_block4a0.PORTAADDR7
address_a[7] => ram_block4a1.PORTAADDR7
address_a[7] => ram_block4a2.PORTAADDR7
address_a[7] => ram_block4a3.PORTAADDR7
address_a[7] => ram_block4a4.PORTAADDR7
address_a[7] => ram_block4a5.PORTAADDR7
address_a[7] => ram_block4a6.PORTAADDR7
address_a[7] => ram_block4a7.PORTAADDR7
address_a[7] => ram_block4a8.PORTAADDR7
address_a[7] => ram_block4a9.PORTAADDR7
address_a[7] => ram_block4a10.PORTAADDR7
address_a[7] => ram_block4a11.PORTAADDR7
address_a[7] => ram_block4a12.PORTAADDR7
address_a[7] => ram_block4a13.PORTAADDR7
address_a[7] => ram_block4a14.PORTAADDR7
address_a[7] => ram_block4a15.PORTAADDR7
address_a[8] => ram_block4a0.PORTAADDR8
address_a[8] => ram_block4a1.PORTAADDR8
address_a[8] => ram_block4a2.PORTAADDR8
address_a[8] => ram_block4a3.PORTAADDR8
address_a[8] => ram_block4a4.PORTAADDR8
address_a[8] => ram_block4a5.PORTAADDR8
address_a[8] => ram_block4a6.PORTAADDR8
address_a[8] => ram_block4a7.PORTAADDR8
address_a[8] => ram_block4a8.PORTAADDR8
address_a[8] => ram_block4a9.PORTAADDR8
address_a[8] => ram_block4a10.PORTAADDR8
address_a[8] => ram_block4a11.PORTAADDR8
address_a[8] => ram_block4a12.PORTAADDR8
address_a[8] => ram_block4a13.PORTAADDR8
address_a[8] => ram_block4a14.PORTAADDR8
address_a[8] => ram_block4a15.PORTAADDR8
address_a[9] => ram_block4a0.PORTAADDR9
address_a[9] => ram_block4a1.PORTAADDR9
address_a[9] => ram_block4a2.PORTAADDR9
address_a[9] => ram_block4a3.PORTAADDR9
address_a[9] => ram_block4a4.PORTAADDR9
address_a[9] => ram_block4a5.PORTAADDR9
address_a[9] => ram_block4a6.PORTAADDR9
address_a[9] => ram_block4a7.PORTAADDR9
address_a[9] => ram_block4a8.PORTAADDR9
address_a[9] => ram_block4a9.PORTAADDR9
address_a[9] => ram_block4a10.PORTAADDR9
address_a[9] => ram_block4a11.PORTAADDR9
address_a[9] => ram_block4a12.PORTAADDR9
address_a[9] => ram_block4a13.PORTAADDR9
address_a[9] => ram_block4a14.PORTAADDR9
address_a[9] => ram_block4a15.PORTAADDR9
address_a[10] => ram_block4a0.PORTAADDR10
address_a[10] => ram_block4a1.PORTAADDR10
address_a[10] => ram_block4a2.PORTAADDR10
address_a[10] => ram_block4a3.PORTAADDR10
address_a[10] => ram_block4a4.PORTAADDR10
address_a[10] => ram_block4a5.PORTAADDR10
address_a[10] => ram_block4a6.PORTAADDR10
address_a[10] => ram_block4a7.PORTAADDR10
address_a[10] => ram_block4a8.PORTAADDR10
address_a[10] => ram_block4a9.PORTAADDR10
address_a[10] => ram_block4a10.PORTAADDR10
address_a[10] => ram_block4a11.PORTAADDR10
address_a[10] => ram_block4a12.PORTAADDR10
address_a[10] => ram_block4a13.PORTAADDR10
address_a[10] => ram_block4a14.PORTAADDR10
address_a[10] => ram_block4a15.PORTAADDR10
address_b[0] => ram_block4a0.PORTBADDR
address_b[0] => ram_block4a1.PORTBADDR
address_b[0] => ram_block4a2.PORTBADDR
address_b[0] => ram_block4a3.PORTBADDR
address_b[0] => ram_block4a4.PORTBADDR
address_b[0] => ram_block4a5.PORTBADDR
address_b[0] => ram_block4a6.PORTBADDR
address_b[0] => ram_block4a7.PORTBADDR
address_b[0] => ram_block4a8.PORTBADDR
address_b[0] => ram_block4a9.PORTBADDR
address_b[0] => ram_block4a10.PORTBADDR
address_b[0] => ram_block4a11.PORTBADDR
address_b[0] => ram_block4a12.PORTBADDR
address_b[0] => ram_block4a13.PORTBADDR
address_b[0] => ram_block4a14.PORTBADDR
address_b[0] => ram_block4a15.PORTBADDR
address_b[1] => ram_block4a0.PORTBADDR1
address_b[1] => ram_block4a1.PORTBADDR1
address_b[1] => ram_block4a2.PORTBADDR1
address_b[1] => ram_block4a3.PORTBADDR1
address_b[1] => ram_block4a4.PORTBADDR1
address_b[1] => ram_block4a5.PORTBADDR1
address_b[1] => ram_block4a6.PORTBADDR1
address_b[1] => ram_block4a7.PORTBADDR1
address_b[1] => ram_block4a8.PORTBADDR1
address_b[1] => ram_block4a9.PORTBADDR1
address_b[1] => ram_block4a10.PORTBADDR1
address_b[1] => ram_block4a11.PORTBADDR1
address_b[1] => ram_block4a12.PORTBADDR1
address_b[1] => ram_block4a13.PORTBADDR1
address_b[1] => ram_block4a14.PORTBADDR1
address_b[1] => ram_block4a15.PORTBADDR1
address_b[2] => ram_block4a0.PORTBADDR2
address_b[2] => ram_block4a1.PORTBADDR2
address_b[2] => ram_block4a2.PORTBADDR2
address_b[2] => ram_block4a3.PORTBADDR2
address_b[2] => ram_block4a4.PORTBADDR2
address_b[2] => ram_block4a5.PORTBADDR2
address_b[2] => ram_block4a6.PORTBADDR2
address_b[2] => ram_block4a7.PORTBADDR2
address_b[2] => ram_block4a8.PORTBADDR2
address_b[2] => ram_block4a9.PORTBADDR2
address_b[2] => ram_block4a10.PORTBADDR2
address_b[2] => ram_block4a11.PORTBADDR2
address_b[2] => ram_block4a12.PORTBADDR2
address_b[2] => ram_block4a13.PORTBADDR2
address_b[2] => ram_block4a14.PORTBADDR2
address_b[2] => ram_block4a15.PORTBADDR2
address_b[3] => ram_block4a0.PORTBADDR3
address_b[3] => ram_block4a1.PORTBADDR3
address_b[3] => ram_block4a2.PORTBADDR3
address_b[3] => ram_block4a3.PORTBADDR3
address_b[3] => ram_block4a4.PORTBADDR3
address_b[3] => ram_block4a5.PORTBADDR3
address_b[3] => ram_block4a6.PORTBADDR3
address_b[3] => ram_block4a7.PORTBADDR3
address_b[3] => ram_block4a8.PORTBADDR3
address_b[3] => ram_block4a9.PORTBADDR3
address_b[3] => ram_block4a10.PORTBADDR3