fpga_dsp_portlink.hier_info

implemention of FPGA and DSP linking port, using Asynchronous mode

|FPGA_DSP_PortLink_BiBus_oneFIFO
TO_DSP[0] <= lpm_bustri1:inst4.tridata[0]
TO_DSP[1] <= lpm_bustri1:inst4.tridata[1]
TO_DSP[2] <= lpm_bustri1:inst4.tridata[2]
TO_DSP[3] <= lpm_bustri1:inst4.tridata[3]
TO_DSP[4] <= lpm_bustri1:inst4.tridata[4]
TO_DSP[5] <= lpm_bustri1:inst4.tridata[5]
TO_DSP[6] <= lpm_bustri1:inst4.tridata[6]
TO_DSP[7] <= lpm_bustri1:inst4.tridata[7]
TO_DSP[8] <= lpm_bustri1:inst4.tridata[8]
TO_DSP[9] <= lpm_bustri1:inst4.tridata[9]
TO_DSP[10] <= lpm_bustri1:inst4.tridata[10]
TO_DSP[11] <= lpm_bustri1:inst4.tridata[11]
TO_DSP[12] <= lpm_bustri1:inst4.tridata[12]
TO_DSP[13] <= lpm_bustri1:inst4.tridata[13]
TO_DSP[14] <= lpm_bustri1:inst4.tridata[14]
TO_DSP[15] <= lpm_bustri1:inst4.tridata[15]
CS => en_blk:inst8.CS
CS => MUX:inst10.CS
CS => inst7.IN0
Addr[0] => en_blk:inst8.Addr[0]
Addr[0] => MUX:inst10.Addr[0]
Addr[1] => en_blk:inst8.Addr[1]
Addr[1] => MUX:inst10.Addr[1]
WE => inst3.IN0
RE => inst6.IN0


|FPGA_DSP_PortLink_BiBus_oneFIFO|lpm_bustri1:inst4
data[0] => lpm_bustri:lpm_bustri_component.data[0]
data[1] => lpm_bustri:lpm_bustri_component.data[1]
data[2] => lpm_bustri:lpm_bustri_component.data[2]
data[3] => lpm_bustri:lpm_bustri_component.data[3]
data[4] => lpm_bustri:lpm_bustri_component.data[4]
data[5] => lpm_bustri:lpm_bustri_component.data[5]
data[6] => lpm_bustri:lpm_bustri_component.data[6]
data[7] => lpm_bustri:lpm_bustri_component.data[7]
data[8] => lpm_bustri:lpm_bustri_component.data[8]
data[9] => lpm_bustri:lpm_bustri_component.data[9]
data[10] => lpm_bustri:lpm_bustri_component.data[10]
data[11] => lpm_bustri:lpm_bustri_component.data[11]
data[12] => lpm_bustri:lpm_bustri_component.data[12]
data[13] => lpm_bustri:lpm_bustri_component.data[13]
data[14] => lpm_bustri:lpm_bustri_component.data[14]
data[15] => lpm_bustri:lpm_bustri_component.data[15]
enabledt => lpm_bustri:lpm_bustri_component.enabledt
enabletr => lpm_bustri:lpm_bustri_component.enabletr
result[0] <= lpm_bustri:lpm_bustri_component.result[0]
result[1] <= lpm_bustri:lpm_bustri_component.result[1]
result[2] <= lpm_bustri:lpm_bustri_component.result[2]
result[3] <= lpm_bustri:lpm_bustri_component.result[3]
result[4] <= lpm_bustri:lpm_bustri_component.result[4]
result[5] <= lpm_bustri:lpm_bustri_component.result[5]
result[6] <= lpm_bustri:lpm_bustri_component.result[6]
result[7] <= lpm_bustri:lpm_bustri_component.result[7]
result[8] <= lpm_bustri:lpm_bustri_component.result[8]
result[9] <= lpm_bustri:lpm_bustri_component.result[9]
result[10] <= lpm_bustri:lpm_bustri_component.result[10]
result[11] <= lpm_bustri:lpm_bustri_component.result[11]
result[12] <= lpm_bustri:lpm_bustri_component.result[12]
result[13] <= lpm_bustri:lpm_bustri_component.result[13]
result[14] <= lpm_bustri:lpm_bustri_component.result[14]
result[15] <= lpm_bustri:lpm_bustri_component.result[15]
tridata[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
tridata[1] <= lpm_bustri:lpm_bustri_component.tridata[1]
tridata[2] <= lpm_bustri:lpm_bustri_component.tridata[2]
tridata[3] <= lpm_bustri:lpm_bustri_component.tridata[3]
tridata[4] <= lpm_bustri:lpm_bustri_component.tridata[4]
tridata[5] <= lpm_bustri:lpm_bustri_component.tridata[5]
tridata[6] <= lpm_bustri:lpm_bustri_component.tridata[6]
tridata[7] <= lpm_bustri:lpm_bustri_component.tridata[7]
tridata[8] <= lpm_bustri:lpm_bustri_component.tridata[8]
tridata[9] <= lpm_bustri:lpm_bustri_component.tridata[9]
tridata[10] <= lpm_bustri:lpm_bustri_component.tridata[10]
tridata[11] <= lpm_bustri:lpm_bustri_component.tridata[11]
tridata[12] <= lpm_bustri:lpm_bustri_component.tridata[12]
tridata[13] <= lpm_bustri:lpm_bustri_component.tridata[13]
tridata[14] <= lpm_bustri:lpm_bustri_component.tridata[14]
tridata[15] <= lpm_bustri:lpm_bustri_component.tridata[15]


|FPGA_DSP_PortLink_BiBus_oneFIFO|lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
tridata[1] <= dout[1]
tridata[2] <= dout[2]
tridata[3] <= dout[3]
tridata[4] <= dout[4]
tridata[5] <= dout[5]
tridata[6] <= dout[6]
tridata[7] <= dout[7]
tridata[8] <= dout[8]
tridata[9] <= dout[9]
tridata[10] <= dout[10]
tridata[11] <= dout[11]
tridata[12] <= dout[12]
tridata[13] <= dout[13]
tridata[14] <= dout[14]
tridata[15] <= dout[15]
data[0] => dout[0].DATAIN
data[1] => dout[1].DATAIN
data[2] => dout[2].DATAIN
data[3] => dout[3].DATAIN
data[4] => dout[4].DATAIN
data[5] => dout[5].DATAIN
data[6] => dout[6].DATAIN
data[7] => dout[7].DATAIN
data[8] => dout[8].DATAIN
data[9] => dout[9].DATAIN
data[10] => dout[10].DATAIN
data[11] => dout[11].DATAIN
data[12] => dout[12].DATAIN
data[13] => dout[13].DATAIN
data[14] => dout[14].DATAIN
data[15] => dout[15].DATAIN
enabletr => din[15].OE
enabletr => din[14].OE
enabletr => din[13].OE
enabletr => din[12].OE
enabletr => din[11].OE
enabletr => din[10].OE
enabletr => din[9].OE
enabletr => din[8].OE
enabletr => din[7].OE
enabletr => din[6].OE
enabletr => din[5].OE
enabletr => din[4].OE
enabletr => din[3].OE
enabletr => din[2].OE
enabletr => din[1].OE
enabletr => din[0].OE
enabledt => dout[15].OE
enabledt => dout[14].OE
enabledt => dout[13].OE
enabledt => dout[12].OE
enabledt => dout[11].OE
enabledt => dout[10].OE
enabledt => dout[9].OE
enabledt => dout[8].OE
enabledt => dout[7].OE
enabledt => dout[6].OE
enabledt => dout[5].OE
enabledt => dout[4].OE
enabledt => dout[3].OE
enabledt => dout[2].OE
enabledt => dout[1].OE
enabledt => dout[0].OE
result[0] <= din[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= din[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= din[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= din[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= din[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= din[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= din[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= din[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= din[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= din[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= din[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= din[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= din[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= din[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= din[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= din[15].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_DSP_PortLink_BiBus_oneFIFO|en_blk:inst8
CS => eno~0.IN0
CS => To_DSP_En~2.IN0
CS => From_DSP_En~0.IN0
Addr[0] => Equal~0.IN3
Addr[0] => Equal~1.IN3
Addr[0] => Equal~2.IN3
Addr[0] => Equal~3.IN3
Addr[1] => Equal~0.IN2
Addr[1] => Equal~1.IN2
Addr[1] => Equal~2.IN2
Addr[1] => Equal~3.IN2
eno <= eno~0.DB_MAX_OUTPUT_PORT_TYPE
To_DSP_En <= To_DSP_En~2.DB_MAX_OUTPUT_PORT_TYPE
From_DSP_En <= From_DSP_En~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10
CS => eno~0.IN0
CS => O1~0.IN0
CS => O1~1.IN0
Addr[0] => Equal~0.IN3
Addr[0] => Equal~1.IN3
Addr[0] => Equal~2.IN3
Addr[1] => Equal~0.IN2
Addr[1] => Equal~1.IN2
Addr[1] => Equal~2.IN2
A1[0] => O1~35.DATAB
A1[1] => O1~33.DATAB
A1[2] => O1~31.DATAB
A1[3] => O1~29.DATAB
A1[4] => O1~27.DATAB
A1[5] => O1~25.DATAB
A1[6] => O1~23.DATAB
A1[7] => O1~21.DATAB
A1[8] => O1~19.DATAB
A1[9] => O1~17.DATAB
A1[10] => O1~15.DATAB
A1[11] => O1~13.DATAB
A1[12] => O1~11.DATAB
A1[13] => O1~9.DATAB
A1[14] => O1~7.DATAB
A1[15] => O1~4.DATAB
A2[0] => O1~34.DATAB
A2[1] => O1~32.DATAB
A2[2] => O1~30.DATAB
A2[3] => O1~28.DATAB
A2[4] => O1~26.DATAB
A2[5] => O1~24.DATAB
A2[6] => O1~22.DATAB
A2[7] => O1~20.DATAB
A2[8] => O1~18.DATAB
A2[9] => O1~16.DATAB
A2[10] => O1~14.DATAB
A2[11] => O1~12.DATAB
A2[12] => O1~10.DATAB
A2[13] => O1~8.DATAB
A2[14] => O1~6.DATAB
A2[15] => O1~2.DATAB
A3[0] => O1~34.DATAA
A3[1] => O1~32.DATAA
A3[2] => O1~30.DATAA
A3[3] => O1~28.DATAA
A3[4] => O1~26.DATAA
A3[5] => O1~24.DATAA
A3[6] => O1~22.DATAA
A3[7] => O1~20.DATAA
A3[8] => O1~18.DATAA
A3[9] => O1~16.DATAA
A3[10] => O1~14.DATAA
A3[11] => O1~12.DATAA
A3[12] => O1~10.DATAA
A3[13] => O1~8.DATAA
A3[14] => O1~6.DATAA
A3[15] => O1~2.DATAA
eno <= eno~0.DB_MAX_OUTPUT_PORT_TYPE
O1[0] <= O1[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[1] <= O1[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[2] <= O1[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[3] <= O1[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[4] <= O1[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[5] <= O1[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[6] <= O1[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[7] <= O1[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[8] <= O1[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[9] <= O1[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[10] <= O1[10]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[11] <= O1[11]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[12] <= O1[12]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[13] <= O1[13]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[14] <= O1[14]$latch.DB_MAX_OUTPUT_PORT_TYPE
O1[15] <= O1[15]$latch.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5
data[0] => dcfifo:dcfifo_component.data[0]
data[1] => dcfifo:dcfifo_component.data[1]
data[2] => dcfifo:dcfifo_component.data[2]
data[3] => dcfifo:dcfifo_component.data[3]
data[4] => dcfifo:dcfifo_component.data[4]
data[5] => dcfifo:dcfifo_component.data[5]
data[6] => dcfifo:dcfifo_component.data[6]
data[7] => dcfifo:dcfifo_component.data[7]
data[8] => dcfifo:dcfifo_component.data[8]
data[9] => dcfifo:dcfifo_component.data[9]
data[10] => dcfifo:dcfifo_component.data[10]
data[11] => dcfifo:dcfifo_component.data[11]
data[12] => dcfifo:dcfifo_component.data[12]
data[13] => dcfifo:dcfifo_component.data[13]
data[14] => dcfifo:dcfifo_component.data[14]
data[15] => dcfifo:dcfifo_component.data[15]
rdclk => dcfifo:dcfifo_component.rdclk
rdreq => dcfifo:dcfifo_component.rdreq
wrclk => dcfifo:dcfifo_component.wrclk
wrreq => dcfifo:dcfifo_component.wrreq
q[0] <= dcfifo:dcfifo_component.q[0]
q[1] <= dcfifo:dcfifo_component.q[1]
q[2] <= dcfifo:dcfifo_component.q[2]
q[3] <= dcfifo:dcfifo_component.q[3]
q[4] <= dcfifo:dcfifo_component.q[4]
q[5] <= dcfifo:dcfifo_component.q[5]
q[6] <= dcfifo:dcfifo_component.q[6]
q[7] <= dcfifo:dcfifo_component.q[7]
q[8] <= dcfifo:dcfifo_component.q[8]
q[9] <= dcfifo:dcfifo_component.q[9]
q[10] <= dcfifo:dcfifo_component.q[10]
q[11] <= dcfifo:dcfifo_component.q[11]
q[12] <= dcfifo:dcfifo_component.q[12]
q[13] <= dcfifo:dcfifo_component.q[13]
q[14] <= dcfifo:dcfifo_component.q[14]
q[15] <= dcfifo:dcfifo_component.q[15]
rdempty <= dcfifo:dcfifo_component.rdempty
wrfull <= dcfifo:dcfifo_component.wrfull


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component
data[0] => dcfifo_fe71:auto_generated.data[0]
data[1] => dcfifo_fe71:auto_generated.data[1]
data[2] => dcfifo_fe71:auto_generated.data[2]
data[3] => dcfifo_fe71:auto_generated.data[3]
data[4] => dcfifo_fe71:auto_generated.data[4]
data[5] => dcfifo_fe71:auto_generated.data[5]
data[6] => dcfifo_fe71:auto_generated.data[6]
data[7] => dcfifo_fe71:auto_generated.data[7]
data[8] => dcfifo_fe71:auto_generated.data[8]
data[9] => dcfifo_fe71:auto_generated.data[9]
data[10] => dcfifo_fe71:auto_generated.data[10]
data[11] => dcfifo_fe71:auto_generated.data[11]
data[12] => dcfifo_fe71:auto_generated.data[12]
data[13] => dcfifo_fe71:auto_generated.data[13]
data[14] => dcfifo_fe71:auto_generated.data[14]
data[15] => dcfifo_fe71:auto_generated.data[15]
q[0] <= dcfifo_fe71:auto_generated.q[0]
q[1] <= dcfifo_fe71:auto_generated.q[1]
q[2] <= dcfifo_fe71:auto_generated.q[2]
q[3] <= dcfifo_fe71:auto_generated.q[3]
q[4] <= dcfifo_fe71:auto_generated.q[4]
q[5] <= dcfifo_fe71:auto_generated.q[5]
q[6] <= dcfifo_fe71:auto_generated.q[6]
q[7] <= dcfifo_fe71:auto_generated.q[7]
q[8] <= dcfifo_fe71:auto_generated.q[8]
q[9] <= dcfifo_fe71:auto_generated.q[9]
q[10] <= dcfifo_fe71:auto_generated.q[10]
q[11] <= dcfifo_fe71:auto_generated.q[11]
q[12] <= dcfifo_fe71:auto_generated.q[12]
q[13] <= dcfifo_fe71:auto_generated.q[13]
q[14] <= dcfifo_fe71:auto_generated.q[14]
q[15] <= dcfifo_fe71:auto_generated.q[15]
rdclk => dcfifo_fe71:auto_generated.rdclk
rdreq => dcfifo_fe71:auto_generated.rdreq
wrclk => dcfifo_fe71:auto_generated.wrclk
wrreq => dcfifo_fe71:auto_generated.wrreq
aclr => ~NO_FANOUT~
rdempty <= dcfifo_fe71:auto_generated.rdempty
rdfull <= <UNC>
wrempty <= <GND>
wrfull <= dcfifo_fe71:auto_generated.wrfull
rdusedw[0] <= <UNC>
rdusedw[1] <= <UNC>
rdusedw[2] <= <UNC>
rdusedw[3] <= <UNC>
rdusedw[4] <= <UNC>
rdusedw[5] <= <UNC>
rdusedw[6] <= <UNC>
rdusedw[7] <= <UNC>
rdusedw[8] <= <UNC>
rdusedw[9] <= <UNC>
rdusedw[10] <= <UNC>
wrusedw[0] <= <GND>
wrusedw[1] <= <GND>
wrusedw[2] <= <GND>
wrusedw[3] <= <GND>
wrusedw[4] <= <GND>
wrusedw[5] <= <GND>
wrusedw[6] <= <GND>
wrusedw[7] <= <GND>
wrusedw[8] <= <GND>
wrusedw[9] <= <GND>
wrusedw[10] <= <GND>


|FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated
data[0] => altsyncram_ofr:fifo_ram.data_a[0]
data[1] => altsyncram_ofr:fifo_ram.data_a[1]
data[2] => altsyncram_ofr:fifo_ram.data_a[2]
data[3] => altsyncram_ofr:fifo_ram.data_a[3]
data[4] => altsyncram_ofr:fifo_ram.data_a[4]
data[5] => altsyncram_ofr:fifo_ram.data_a[5]
data[6] => altsyncram_ofr:fifo_ram.data_a[6]
data[7] => altsyncram_ofr:fifo_ram.data_a[7]
data[8] => altsyncram_ofr:fifo_ram.data_a[8]
data[9] => altsyncram_ofr:fifo_ram.data_a[9]
data[10] => altsyncram_ofr:fifo_ram.data_a[10]
data[11] => altsyncram_ofr:fifo_ram.data_a[11]
data[12] => altsyncram_ofr:fifo_ram.data_a[12]
data[13] => altsyncram_ofr:fifo_ram.data_a[13]
data[14] => altsyncram_ofr:fifo_ram.data_a[14]
data[15] => altsyncram_ofr:fifo_ram.data_a[15]
q[0] <= altsyncram_ofr:fifo_ram.q_b[0]
q[1] <= altsyncram_ofr:fifo_ram.q_b[1]
q[2] <= altsyncram_ofr:fifo_ram.q_b[2]
q[3] <= altsyncram_ofr:fifo_ram.q_b[3]
q[4] <= altsyncram_ofr:fifo_ram.q_b[4]
q[5] <= altsyncram_ofr:fifo_ram.q_b[5]
q[6] <= altsyncram_ofr:fifo_ram.q_b[6]
q[7] <= altsyncram_ofr:fifo_ram.q_b[7]
q[8] <= altsyncram_ofr:fifo_ram.q_b[8]
q[9] <= altsyncram_ofr:fifo_ram.q_b[9]
q[10] <= altsyncram_ofr:fifo_ram.q_b[10]
q[11] <= altsyncram_ofr:fifo_ram.q_b[11]
q[12] <= altsyncram_ofr:fifo_ram.q_b[12]
q[13] <= altsyncram_ofr:fifo_ram.q_b[13]
q[14] <= altsyncram_ofr:fifo_ram.q_b[14]
q[15] <= altsyncram_ofr:fifo_ram.q_b[15]
rdclk => a_graycounter_p96:rdptr_g1p.clock
rdclk => altsyncram_ofr:fifo_ram.clock1
rdclk => alt_synch_pipe_hv7:rs_dgwp.clock
rdclk => p0addr.CLK
rdclk => rdptr_g[10].CLK
rdclk => rdptr_g[9].CLK
rdclk => rdptr_g[8].CLK