a_graycounter_b86.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--a_graycounter DEVICE_FAMILY="Cyclone II" WIDTH=4 aclr clock cnt_en q
--VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:27:12:26:10:SJ cbx_a_graycounter 2005:07:27:11:56:48:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_flex10ke 2002:10:19:11:54:38:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


--  Copyright (C) 1991-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
WITH ( 	LUT_MASK,	SUM_LUTC_INPUT) 
RETURNS ( combout, cout);
FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
RETURNS ( regout);

--synthesis_resources = lut 5 reg 5 
SUBDESIGN a_graycounter_b86
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[3..0]	:	output;
) 
VARIABLE 
	countera0 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "C6A0",
			SUM_LUTC_INPUT = "cin"
		);
	countera1 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "6C50",
			SUM_LUTC_INPUT = "cin"
		);
	countera2 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "6C50",
			SUM_LUTC_INPUT = "cin"
		);
	countera3 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A5A",
			SUM_LUTC_INPUT = "cin"
		);
	parity : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "6682"
		);
	counter_ffa[3..0] : cycloneii_lcell_ff;
	parity_ff : cycloneii_lcell_ff;
	power_modified_counter_values[3..0]	: WIRE;
	sclr	: NODE;
	updown	: NODE;

BEGIN 
	countera[3..0].cin = ( countera[2..0].cout, parity.cout);
	countera[3..0].dataa = ( power_modified_counter_values[3..3], power_modified_counter_values[1..0], cnt_en);
	countera[0].datab = counter_ffa[0].regout;
	countera[1].datab = power_modified_counter_values[1..1];
	countera[2].datab = power_modified_counter_values[2..2];
	countera[3..0].datad = B"1111";
	parity.cin = updown;
	parity.dataa = cnt_en;
	parity.datab = parity_ff.regout;
	parity.datad = B"1";
	counter_ffa[].aclr = aclr;
	counter_ffa[].clk = clock;
	counter_ffa[].datain = countera[3..0].combout;
	counter_ffa[].sclr = sclr;
	parity_ff.aclr = aclr;
	parity_ff.clk = clock;
	parity_ff.datain = parity.combout;
	parity_ff.sclr = sclr;
	power_modified_counter_values[] = ( counter_ffa[3..0].regout);
	q[] = power_modified_counter_values[];
	sclr = GND;
	updown = VCC;
END;
--VALID FILE