cmpr_rag.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


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--synthesis_resources = lut 5 
SUBDESIGN cmpr_rag
( 
	aeb	:	output;
	dataa[7..0]	:	input;
	datab[7..0]	:	input;
) 
VARIABLE
	aeb_int	:	WIRE;
BEGIN 
	IF (dataa[] == datab[]) THEN
		aeb_int = VCC;
	ELSE
		aeb_int = GND;
	END IF;
	aeb = aeb_int;
END;
--VALID FILE