add_sub_t5c.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=4 dataa datab result
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


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FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);

--synthesis_resources = lut 4 
SUBDESIGN add_sub_t5c
( 
	dataa[3..0]	:	input;
	datab[3..0]	:	input;
	result[3..0]	:	output;
) 
VARIABLE 
	add_sub_cella[3..0] : carry_sum;
	datab_node[3..0]	: WIRE;
	main_cin_wire	: WIRE;

BEGIN 
	add_sub_cella[].cin = ( ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
	add_sub_cella[].sin = ( ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
	datab_node[] = (! datab[]);
	main_cin_wire = B"1";
	result[] = add_sub_cella[].sout;
END;
--VALID FILE