a_gray2bin_7cb.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--a_gray2bin carry_chain="MANUAL" carry_chain_length=48 device_family="Cyclone II" ignore_carry_buffers="OFF" WIDTH=4 bin gray
--VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:27:12:26:10:SJ cbx_mgl 2005:10:09:07:39:04:SJ  VERSION_END


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--synthesis_resources = 
SUBDESIGN a_gray2bin_7cb
( 
	bin[3..0]	:	output;
	gray[3..0]	:	input;
) 
VARIABLE 
	xor0	: WIRE;
	xor1	: WIRE;
	xor2	: WIRE;

BEGIN 
	bin[] = ( gray[3..3], xor2, xor1, xor0);
	xor0 = (gray[0..0] $ xor1);
	xor1 = (gray[1..1] $ xor2);
	xor2 = (gray[3..3] $ gray[2..2]);
END;
--VALID FILE