a_dpfifo_jir.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=4 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=2 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty full q rreq sclr usedw wreq lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K"
--VERSION_BEGIN 5.1 cbx_altdpram 2004:12:01:07:29:56:SJ cbx_altsyncram 2005:10:21:05:19:54:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_fifo_common 2005:07:22:05:40:24:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_counter 2005:08:24:10:49:38:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_scfifo 2005:09:07:08:25:24:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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FUNCTION altsyncram_7e61 (address_a[1..0], address_b[1..0], clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION cntr_678 (clock, cnt_en, sclr)
RETURNS ( q[0..0]);
FUNCTION cntr_l57 (clock, cnt_en, sclr, updown)
RETURNS ( q[1..0]);
FUNCTION cntr_778 (clock, cnt_en, sclr)
RETURNS ( q[1..0]);

--synthesis_resources = lut 2 reg 8 
SUBDESIGN a_dpfifo_jir
( 
	clock	:	input;
	data[15..0]	:	input;
	empty	:	output;
	full	:	output;
	q[15..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[1..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	FIFOram : altsyncram_7e61;
	empty_dff : dffe;
	full_dff : dffe;
	low_addressa[1..0] : dffe;
	rd_ptr_lsb : dffe;
	usedw_is_0_dff : dffe;
	usedw_is_1_dff : dffe;
	wrreq_delay : dffe;
	almost_full_comparer_aeb_int	:	WIRE;
	almost_full_comparer_aeb	:	WIRE;
	almost_full_comparer_dataa[1..0]	:	WIRE;
	almost_full_comparer_datab[1..0]	:	WIRE;
	two_comparison_aeb_int	:	WIRE;
	two_comparison_aeb	:	WIRE;
	two_comparison_dataa[1..0]	:	WIRE;
	two_comparison_datab[1..0]	:	WIRE;
	rd_ptr_msb : cntr_678;
	usedw_counter : cntr_l57;
	wr_ptr : cntr_778;
	aclr	: NODE;
	asynch_read_counter_enable	: WIRE;
	empty_out	: WIRE;
	full_out	: WIRE;
	pulse_ram_output	: WIRE;
	ram_read_address[1..0]	: WIRE;
	rd_ptr[1..0]	: WIRE;
	usedw_is_0	: WIRE;
	usedw_is_1	: WIRE;
	usedw_is_2	: WIRE;
	usedw_will_be_0	: WIRE;
	usedw_will_be_1	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wait_state	: WIRE;

BEGIN 
	FIFOram.address_a[] = wr_ptr.q[];
	FIFOram.address_b[] = ram_read_address[];
	FIFOram.clock0 = clock;
	FIFOram.clock1 = clock;
	FIFOram.clocken1 = pulse_ram_output;
	FIFOram.data_a[] = data[];
	FIFOram.wren_a = valid_wreq;
	empty_dff.CLK = clock;
	empty_dff.CLRN = (! aclr);
	empty_dff.D = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
	full_dff.CLK = clock;
	full_dff.CLRN = (! aclr);
	full_dff.D = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer_aeb) # (full_dff.Q & (! (valid_wreq $ valid_rreq)))));
	low_addressa[].CLK = clock;
	low_addressa[].CLRN = (! aclr);
	low_addressa[].D = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].Q)));
	rd_ptr_lsb.CLK = clock;
	rd_ptr_lsb.CLRN = (! aclr);
	rd_ptr_lsb.D = ((! rd_ptr_lsb.Q) & (! sclr));
	rd_ptr_lsb.ENA = (asynch_read_counter_enable # sclr);
	usedw_is_0_dff.CLK = clock;
	usedw_is_0_dff.CLRN = (! aclr);
	usedw_is_0_dff.D = (! usedw_will_be_0);
	usedw_is_1_dff.CLK = clock;
	usedw_is_1_dff.CLRN = (! aclr);
	usedw_is_1_dff.D = usedw_will_be_1;
	wrreq_delay.CLK = clock;
	wrreq_delay.CLRN = (! aclr);
	wrreq_delay.D = ((! sclr) & valid_wreq);
	IF (almost_full_comparer_dataa[] == almost_full_comparer_datab[]) THEN
		almost_full_comparer_aeb_int = VCC;
	ELSE
		almost_full_comparer_aeb_int = GND;
	END IF;
	almost_full_comparer_aeb = almost_full_comparer_aeb_int;
	almost_full_comparer_dataa[] = B"11";
	almost_full_comparer_datab[] = usedw_counter.q[];
	IF (two_comparison_dataa[] == two_comparison_datab[]) THEN
		two_comparison_aeb_int = VCC;
	ELSE
		two_comparison_aeb_int = GND;
	END IF;
	two_comparison_aeb = two_comparison_aeb_int;
	two_comparison_dataa[] = usedw_counter.q[];
	two_comparison_datab[] = ( B"1", B"0");
	rd_ptr_msb.clock = clock;
	rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.Q));
	rd_ptr_msb.sclr = sclr;
	usedw_counter.clock = clock;
	usedw_counter.cnt_en = (valid_wreq $ valid_rreq);
	usedw_counter.sclr = sclr;
	usedw_counter.updown = valid_wreq;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	aclr = GND;
	asynch_read_counter_enable = pulse_ram_output;
	empty = empty_out;
	empty_out = (! empty_dff.Q);
	full = full_out;
	full_out = full_dff.Q;
	pulse_ram_output = valid_rreq;
	q[] = FIFOram.q_b[];
	ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].Q) # (asynch_read_counter_enable & rd_ptr[]));
	rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.Q));
	usedw[] = usedw_counter.q[];
	usedw_is_0 = (! usedw_is_0_dff.Q);
	usedw_is_1 = usedw_is_1_dff.Q;
	usedw_is_2 = two_comparison_aeb;
	usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
	usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))));
	valid_rreq = (rreq & (! empty_out));
	valid_wreq = (wreq & (! full_out));
	wait_state = (usedw_will_be_1 & valid_wreq);
END;
--VALID FILE