fpga_dsp_portlink_bibus.vwf

来自「implemention of FPGA and DSP linking por」· VWF 代码 · 共 2,367 行 · 第 1/3 页

VWF
2,367 行
字号
123
		LEVEL 1 FOR 10.0;
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		{
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			LEVEL 0 FOR 10.0;
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		LEVEL 1 FOR 10.0;
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		LEVEL 1 FOR 10.0;
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		{
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TRANSITION_LIST("DATAin[15]")
{
	NODE
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TRANSITION_LIST("DATAin[14]")
{
	NODE
	{
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		LEVEL 0 FOR 1000.0;
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}

TRANSITION_LIST("DATAin[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
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}

TRANSITION_LIST("DATAin[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATAin[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATAin[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATAin[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATAin[8]")
{
	NODE
	{
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		LEVEL 1 FOR 70.0;
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}

TRANSITION_LIST("DATAin[7]")
{
	NODE
	{
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		LEVEL 0 FOR 520.0;
		LEVEL 1 FOR 140.0;
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}

TRANSITION_LIST("DATAin[6]")
{
	NODE
	{
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		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 100.0;
		LEVEL 0 FOR 340.0;
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}

TRANSITION_LIST("DATAin[5]")
{
	NODE
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}

TRANSITION_LIST("DATAin[4]")
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	NODE
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		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 340.0;
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}

TRANSITION_LIST("DATAin[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 510.0;
		LEVEL 1 FOR 80.0;
		LEVEL 0 FOR 410.0;
	}
}

TRANSITION_LIST("DATAin[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 470.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 340.0;
	}
}

TRANSITION_LIST("DATAin[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 450.0;
		LEVEL 1 FOR 20.0;
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		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
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		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 340.0;
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}

TRANSITION_LIST("DATAin[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 440.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 350.0;
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}

TRANSITION_LIST("Dataout[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
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}

TRANSITION_LIST("Dataout[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
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}

TRANSITION_LIST("Dataout[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
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}

TRANSITION_LIST("Dataout[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
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}

TRANSITION_LIST("Dataout[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
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}

TRANSITION_LIST("Dataout[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Dataout[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Rclk_in")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 36;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
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		NODE
		{
			REPEAT = 1;
			LEVEL 0 FOR 35.0;
		}
		LEVEL 1 FOR 5.0;
		NODE
		{
			REPEAT = 60;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("RE")
{
	NODE
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		REPEAT = 1;
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		LEVEL 1 FOR 33.7;
		LEVEL 0 FOR 6.3;
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		LEVEL 0 FOR 6.3;
		LEVEL 1 FOR 33.7;
		LEVEL 0 FOR 6.3;
		LEVEL 1 FOR 103.7;
		LEVEL 0 FOR 6.3;
		LEVEL 1 FOR 54.28;
		LEVEL 0 FOR 5.4;
		LEVEL 1 FOR 244.6;
		LEVEL 0 FOR 5.4;
		LEVEL 1 FOR 14.6;
		LEVEL 0 FOR 5.4;
		LEVEL 1 FOR 14.6;
		LEVEL 0 FOR 5.4;
		LEVEL 1 FOR 14.26;
		LEVEL 0 FOR 5.2;
		LEVEL 1 FOR 15.14;
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		LEVEL 1 FOR 15.14;
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		LEVEL 0 FOR 5.4;
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		LEVEL 0 FOR 5.2;
		LEVEL 1 FOR 15.14;
		LEVEL 0 FOR 5.4;
		LEVEL 1 FOR 14.26;
		LEVEL 0 FOR 5.2;
		LEVEL 1 FOR 22.76;
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}

TRANSITION_LIST("Ren_in")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 650.0;
	}
}

TRANSITION_LIST("TO_DSP[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
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		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
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		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
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}

TRANSITION_LIST("TO_DSP[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
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}

TRANSITION_LIST("TO_DSP[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 610.0;
	}
}

TRANSITION_LIST("TO_DSP[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL Z FOR 100.0;
		LEVEL 0 FOR 10.0;
123

fpga_dsp_portlink_bibus.vwf - 源码说明

本页面展示了「implemention of FPGA and DSP linking port, using Asynchronous mode」中的 fpga_dsp_portlink_bibus.vwf 源码文件，采用 VWF 编程语言编写，共 2,367 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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