fpga_dsp_portlink.tan.summary

implemention of FPGA and DSP linking port, using Asynchronous mode

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.077 ns
From           : Addr[0]
To             : FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]
From Clock     : --
To Clock       : RE
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.407 ns
From           : MUX:inst10|O1[0]
To             : TO_DSP[0]
From Clock     : Addr[0]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.722 ns
From           : Addr[0]
To             : TO_DSP[4]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.869 ns
From           : CS
To             : MUX:inst10|O1[2]
From Clock     : --
To Clock       : Addr[0]
Failed Paths   : 0

Type           : Clock Setup: 'WE'
Slack          : N/A
Required Time  : None
Actual Time    : 132.59 MHz ( period = 7.542 ns )
From           : FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9]
To             : FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg
From Clock     : WE
To Clock       : WE
Failed Paths   : 0

Type           : Clock Setup: 'RE'
Slack          : N/A
Required Time  : None
Actual Time    : 156.05 MHz ( period = 6.408 ns )
From           : FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10]
To             : FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]
From Clock     : RE
To Clock       : RE
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------