📄 fpga_dsp_portlink.bdf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.3"))
(pin
(input)
(rect -432 128 -232 144)
(text "INPUT" (rect 165 0 193 10)(font "Arial" (font_size 6)))
(text "DATA_FromDSP[15..0]" (rect 5 0 119 12)(font "Arial" ))
(pt 200 8)
(drawing
(line (pt 124 12)(pt 149 12)(line_width 1))
(line (pt 124 4)(pt 149 4)(line_width 1))
(line (pt 153 8)(pt 200 8)(line_width 1))
(line (pt 124 12)(pt 124 4)(line_width 1))
(line (pt 149 4)(pt 153 8)(line_width 1))
(line (pt 149 12)(pt 153 8)(line_width 1))
)
(text "VCC" (rect 168 7 188 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect -400 144 -232 160)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "WE" (rect 5 0 22 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect -400 160 -232 176)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "CS" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect -400 176 -232 192)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "RE" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect -400 112 -232 128)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "Addr[1..0]" (rect 5 0 53 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 136 112 331 128)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DATA_ToDSP[15..0]" (rect 90 0 190 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
)
(symbol
(rect -192 88 104 216)
(text "FPGA_DSP_PortLink_Inner" (rect 5 0 156 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "Addr[1..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "Addr[1..0]" (rect 21 27 77 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "DATA_FromDSP[15..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
(text "DATA_FromDSP[15..0]" (rect 21 43 149 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "WE" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "WE" (rect 21 59 39 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "CS" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "CS" (rect 21 75 37 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "RE" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "RE" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 296 32)
(output)
(text "DATA_ToDSP[15..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
(text "DATA_ToDSP[15..0]" (rect 161 27 275 41)(font "Arial" (font_size 8)))
(line (pt 296 32)(pt 280 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 280 112)(line_width 1))
)
)
(connector
(pt 104 120)
(pt 136 120)
(bus)
)
(connector
(pt -232 136)
(pt -192 136)
(bus)
)
(connector
(pt -232 120)
(pt -192 120)
(bus)
)
(connector
(pt -232 152)
(pt -192 152)
)
(connector
(pt -232 168)
(pt -192 168)
)
(connector
(pt -232 184)
(pt -192 184)
)
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