fpga_dsp_portlink.map.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

--R1_dffe10a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[1]
R1_dffe10a[1] = DFFEAS(R1_dffe9a[1], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[1]
M1_power_modified_counter_values[1] = DFFEAS(M1_countera1, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[3]
M1_power_modified_counter_values[3] = DFFEAS(M1_countera3, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L44 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~82
H1L44 = R1_dffe10a[3] & M1_power_modified_counter_values[3] & (R1_dffe10a[1] $ !M1_power_modified_counter_values[1]) # !R1_dffe10a[3] & !M1_power_modified_counter_values[3] & (R1_dffe10a[1] $ !M1_power_modified_counter_values[1]);


--R1_dffe10a[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[5]
R1_dffe10a[5] = DFFEAS(R1_dffe9a[5], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[5]
M1_power_modified_counter_values[5] = DFFEAS(M1_countera5, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L38 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0
H1L38 = H1L43 & H1L44 & (R1_dffe10a[5] $ !M1_power_modified_counter_values[5]);


--E1L32 is MUX:inst10|O1~524
E1L32 = Addr[0] & !CS;


--E1L33 is MUX:inst10|O1~525
E1L33 = E1L32 & (H1L38 & !Addr[1]) # !E1L32 & P1_q_a[1];


--P1_q_a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[0]_PORT_A_data_in = VCC;
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_data_in = A1L38;
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = !RE;
P1_q_a[0]_clock_1 = !WE;
P1_q_a[0]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, P1_q_a[0]_clock_enable_0, , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0] = P1_q_a[0]_PORT_A_data_out_reg[0];


--H1_rdptr_g[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[2]
H1_rdptr_g[2] = DFFEAS(K1_power_modified_counter_values[2], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[4]
H1_rdptr_g[4] = DFFEAS(K1_power_modified_counter_values[4], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[4]
Q1_dffe7a[4] = DFFEAS(Q1_dffe6a[4], !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[2]
Q1_dffe7a[2] = DFFEAS(Q1_dffe6a[2], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L17 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~71
H1L17 = H1_rdptr_g[2] & Q1_dffe7a[2] & (H1_rdptr_g[4] $ !Q1_dffe7a[4]) # !H1_rdptr_g[2] & !Q1_dffe7a[2] & (H1_rdptr_g[4] $ !Q1_dffe7a[4]);


--H1_rdptr_g[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[8]
H1_rdptr_g[8] = DFFEAS(K1_power_modified_counter_values[8], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[10]
H1_rdptr_g[10] = DFFEAS(K1_power_modified_counter_values[10], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10]
Q1_dffe7a[10] = DFFEAS(Q1_dffe6a[10], !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[8]
Q1_dffe7a[8] = DFFEAS(Q1_dffe6a[8], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L18 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72
H1L18 = H1_rdptr_g[8] & Q1_dffe7a[8] & (H1_rdptr_g[10] $ !Q1_dffe7a[10]) # !H1_rdptr_g[8] & !Q1_dffe7a[8] & (H1_rdptr_g[10] $ !Q1_dffe7a[10]);


--H1_rdptr_g[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[9]
H1_rdptr_g[9] = DFFEAS(K1_power_modified_counter_values[9], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[0]
H1_rdptr_g[0] = DFFEAS(K1_power_modified_counter_values[0], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[0]
Q1_dffe7a[0] = DFFEAS(Q1_dffe6a[0], !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[9]
Q1_dffe7a[9] = DFFEAS(Q1_dffe6a[9], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L19 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~73
H1L19 = H1_rdptr_g[9] & Q1_dffe7a[9] & (H1_rdptr_g[0] $ !Q1_dffe7a[0]) # !H1_rdptr_g[9] & !Q1_dffe7a[9] & (H1_rdptr_g[0] $ !Q1_dffe7a[0]);


--H1_rdptr_g[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[6]
H1_rdptr_g[6] = DFFEAS(K1_power_modified_counter_values[6], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[7]
H1_rdptr_g[7] = DFFEAS(K1_power_modified_counter_values[7], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[7]
Q1_dffe7a[7] = DFFEAS(Q1_dffe6a[7], !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[6]
Q1_dffe7a[6] = DFFEAS(Q1_dffe6a[6], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L20 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~74
H1L20 = H1_rdptr_g[6] & Q1_dffe7a[6] & (H1_rdptr_g[7] $ !Q1_dffe7a[7]) # !H1_rdptr_g[6] & !Q1_dffe7a[6] & (H1_rdptr_g[7] $ !Q1_dffe7a[7]);


--H1L21 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75
H1L21 = H1L17 & H1L18 & H1L19 & H1L20;


--H1_rdptr_g[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[3]
H1_rdptr_g[3] = DFFEAS(K1_power_modified_counter_values[3], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[1]
H1_rdptr_g[1] = DFFEAS(K1_power_modified_counter_values[1], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[1]
Q1_dffe7a[1] = DFFEAS(Q1_dffe6a[1], !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[3]
Q1_dffe7a[3] = DFFEAS(Q1_dffe6a[3], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L22 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~76
H1L22 = H1_rdptr_g[3] & Q1_dffe7a[3] & (H1_rdptr_g[1] $ !Q1_dffe7a[1]) # !H1_rdptr_g[3] & !Q1_dffe7a[3] & (H1_rdptr_g[1] $ !Q1_dffe7a[1]);


--H1_rdptr_g[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[5]
H1_rdptr_g[5] = DFFEAS(K1_power_modified_counter_values[5], !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[5]
Q1_dffe7a[5] = DFFEAS(Q1_dffe6a[5], !RE,  ,  ,  ,  ,  ,  ,  );


--H1L16 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0
H1L16 = H1L21 & H1L22 & (H1_rdptr_g[5] $ !Q1_dffe7a[5]);