fpga_dsp_portlink.map.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

P1_q_a[4]_PORT_A_data_out = MEMORY(P1_q_a[4]_PORT_A_data_in_reg, P1_q_a[4]_PORT_B_data_in_reg, P1_q_a[4]_PORT_A_address_reg, P1_q_a[4]_PORT_B_address_reg, P1_q_a[4]_PORT_A_write_enable_reg, P1_q_a[4]_PORT_B_write_enable_reg, , , P1_q_a[4]_clock_0, P1_q_a[4]_clock_1, P1_q_a[4]_clock_enable_0, , , );
P1_q_a[4]_PORT_A_data_out_reg = DFFE(P1_q_a[4]_PORT_A_data_out, P1_q_a[4]_clock_0, , , P1_q_a[4]_clock_enable_0);
P1_q_a[4] = P1_q_a[4]_PORT_A_data_out_reg[0];


--E1L29 is MUX:inst10|O1~521
E1L29 = P1_q_a[4] & (CS # !Addr[0]);


--P1_q_a[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[3]_PORT_A_data_in = VCC;
P1_q_a[3]_PORT_A_data_in_reg = DFFE(P1_q_a[3]_PORT_A_data_in, P1_q_a[3]_clock_0, , , P1_q_a[3]_clock_enable_0);
P1_q_a[3]_PORT_B_data_in = A1L35;
P1_q_a[3]_PORT_B_data_in_reg = DFFE(P1_q_a[3]_PORT_B_data_in, P1_q_a[3]_clock_1, , , );
P1_q_a[3]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[3]_PORT_A_address_reg = DFFE(P1_q_a[3]_PORT_A_address, P1_q_a[3]_clock_0, , , P1_q_a[3]_clock_enable_0);
P1_q_a[3]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[3]_PORT_B_address_reg = DFFE(P1_q_a[3]_PORT_B_address, P1_q_a[3]_clock_1, , , );
P1_q_a[3]_PORT_A_write_enable = GND;
P1_q_a[3]_PORT_A_write_enable_reg = DFFE(P1_q_a[3]_PORT_A_write_enable, P1_q_a[3]_clock_0, , , P1_q_a[3]_clock_enable_0);
P1_q_a[3]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[3]_PORT_B_write_enable_reg = DFFE(P1_q_a[3]_PORT_B_write_enable, P1_q_a[3]_clock_1, , , );
P1_q_a[3]_clock_0 = !RE;
P1_q_a[3]_clock_1 = !WE;
P1_q_a[3]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[3]_PORT_A_data_out = MEMORY(P1_q_a[3]_PORT_A_data_in_reg, P1_q_a[3]_PORT_B_data_in_reg, P1_q_a[3]_PORT_A_address_reg, P1_q_a[3]_PORT_B_address_reg, P1_q_a[3]_PORT_A_write_enable_reg, P1_q_a[3]_PORT_B_write_enable_reg, , , P1_q_a[3]_clock_0, P1_q_a[3]_clock_1, P1_q_a[3]_clock_enable_0, , , );
P1_q_a[3]_PORT_A_data_out_reg = DFFE(P1_q_a[3]_PORT_A_data_out, P1_q_a[3]_clock_0, , , P1_q_a[3]_clock_enable_0);
P1_q_a[3] = P1_q_a[3]_PORT_A_data_out_reg[0];


--E1L30 is MUX:inst10|O1~522
E1L30 = P1_q_a[3] & (CS # !Addr[0]);


--P1_q_a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[2]_PORT_A_data_in = VCC;
P1_q_a[2]_PORT_A_data_in_reg = DFFE(P1_q_a[2]_PORT_A_data_in, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_data_in = A1L36;
P1_q_a[2]_PORT_B_data_in_reg = DFFE(P1_q_a[2]_PORT_B_data_in, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[2]_PORT_A_address_reg = DFFE(P1_q_a[2]_PORT_A_address, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[2]_PORT_B_address_reg = DFFE(P1_q_a[2]_PORT_B_address, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_write_enable = GND;
P1_q_a[2]_PORT_A_write_enable_reg = DFFE(P1_q_a[2]_PORT_A_write_enable, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[2]_PORT_B_write_enable_reg = DFFE(P1_q_a[2]_PORT_B_write_enable, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_clock_0 = !RE;
P1_q_a[2]_clock_1 = !WE;
P1_q_a[2]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[2]_PORT_A_data_out = MEMORY(P1_q_a[2]_PORT_A_data_in_reg, P1_q_a[2]_PORT_B_data_in_reg, P1_q_a[2]_PORT_A_address_reg, P1_q_a[2]_PORT_B_address_reg, P1_q_a[2]_PORT_A_write_enable_reg, P1_q_a[2]_PORT_B_write_enable_reg, , , P1_q_a[2]_clock_0, P1_q_a[2]_clock_1, P1_q_a[2]_clock_enable_0, , , );
P1_q_a[2]_PORT_A_data_out_reg = DFFE(P1_q_a[2]_PORT_A_data_out, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2] = P1_q_a[2]_PORT_A_data_out_reg[0];


--E1L31 is MUX:inst10|O1~523
E1L31 = P1_q_a[2] & (CS # !Addr[0]);


--P1_q_a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[1]_PORT_A_data_in = VCC;
P1_q_a[1]_PORT_A_data_in_reg = DFFE(P1_q_a[1]_PORT_A_data_in, P1_q_a[1]_clock_0, , , P1_q_a[1]_clock_enable_0);
P1_q_a[1]_PORT_B_data_in = A1L37;
P1_q_a[1]_PORT_B_data_in_reg = DFFE(P1_q_a[1]_PORT_B_data_in, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[1]_PORT_A_address_reg = DFFE(P1_q_a[1]_PORT_A_address, P1_q_a[1]_clock_0, , , P1_q_a[1]_clock_enable_0);
P1_q_a[1]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[1]_PORT_B_address_reg = DFFE(P1_q_a[1]_PORT_B_address, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_PORT_A_write_enable = GND;
P1_q_a[1]_PORT_A_write_enable_reg = DFFE(P1_q_a[1]_PORT_A_write_enable, P1_q_a[1]_clock_0, , , P1_q_a[1]_clock_enable_0);
P1_q_a[1]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[1]_PORT_B_write_enable_reg = DFFE(P1_q_a[1]_PORT_B_write_enable, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_clock_0 = !RE;
P1_q_a[1]_clock_1 = !WE;
P1_q_a[1]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[1]_PORT_A_data_out = MEMORY(P1_q_a[1]_PORT_A_data_in_reg, P1_q_a[1]_PORT_B_data_in_reg, P1_q_a[1]_PORT_A_address_reg, P1_q_a[1]_PORT_B_address_reg, P1_q_a[1]_PORT_A_write_enable_reg, P1_q_a[1]_PORT_B_write_enable_reg, , , P1_q_a[1]_clock_0, P1_q_a[1]_clock_1, P1_q_a[1]_clock_enable_0, , , );
P1_q_a[1]_PORT_A_data_out_reg = DFFE(P1_q_a[1]_PORT_A_data_out, P1_q_a[1]_clock_0, , , P1_q_a[1]_clock_enable_0);
P1_q_a[1] = P1_q_a[1]_PORT_A_data_out_reg[0];


--R1_dffe10a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[2]
R1_dffe10a[2] = DFFEAS(R1_dffe9a[2], !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[4]
R1_dffe10a[4] = DFFEAS(R1_dffe9a[4], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[4]
M1_power_modified_counter_values[4] = DFFEAS(M1_countera4, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[2]
M1_power_modified_counter_values[2] = DFFEAS(M1_countera2, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L39 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~77
H1L39 = R1_dffe10a[2] & M1_power_modified_counter_values[2] & (R1_dffe10a[4] $ !M1_power_modified_counter_values[4]) # !R1_dffe10a[2] & !M1_power_modified_counter_values[2] & (R1_dffe10a[4] $ !M1_power_modified_counter_values[4]);


--R1_dffe10a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[8]
R1_dffe10a[8] = DFFEAS(R1_dffe9a[8], !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[10]
R1_dffe10a[10] = DFFEAS(R1_dffe9a[10], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10]
M1_power_modified_counter_values[10] = DFFEAS(M1_countera10, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[8]
M1_power_modified_counter_values[8] = DFFEAS(M1_countera8, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L40 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~78
H1L40 = R1_dffe10a[8] & M1_power_modified_counter_values[8] & (R1_dffe10a[10] $ !M1_power_modified_counter_values[10]) # !R1_dffe10a[8] & !M1_power_modified_counter_values[8] & (R1_dffe10a[10] $ !M1_power_modified_counter_values[10]);


--R1_dffe10a[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[9]
R1_dffe10a[9] = DFFEAS(R1_dffe9a[9], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9]
M1_power_modified_counter_values[9] = DFFEAS(M1_countera9, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[0]
R1_dffe10a[0] = DFFEAS(R1_dffe9a[0], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_counter_ffa[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|counter_ffa[0]
M1_counter_ffa[0] = DFFEAS(M1_countera0, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L41 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79
H1L41 = R1_dffe10a[9] & M1_power_modified_counter_values[9] & (R1_dffe10a[0] $ M1_counter_ffa[0]) # !R1_dffe10a[9] & !M1_power_modified_counter_values[9] & (R1_dffe10a[0] $ M1_counter_ffa[0]);


--R1_dffe10a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[6]
R1_dffe10a[6] = DFFEAS(R1_dffe9a[6], !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[7]
R1_dffe10a[7] = DFFEAS(R1_dffe9a[7], !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[7]
M1_power_modified_counter_values[7] = DFFEAS(M1_countera7, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[6]
M1_power_modified_counter_values[6] = DFFEAS(M1_countera6, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L42 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~80
H1L42 = R1_dffe10a[6] & M1_power_modified_counter_values[6] & (R1_dffe10a[7] $ !M1_power_modified_counter_values[7]) # !R1_dffe10a[6] & !M1_power_modified_counter_values[6] & (R1_dffe10a[7] $ !M1_power_modified_counter_values[7]);


--H1L43 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81
H1L43 = H1L39 & H1L40 & H1L41 & H1L42;


--R1_dffe10a[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[3]
R1_dffe10a[3] = DFFEAS(R1_dffe9a[3], !WE,  ,  ,  ,  ,  ,  ,  );