fpga_dsp_portlink.map.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

P1_q_a[10]_PORT_B_write_enable_reg = DFFE(P1_q_a[10]_PORT_B_write_enable, P1_q_a[10]_clock_1, , , );
P1_q_a[10]_clock_0 = !RE;
P1_q_a[10]_clock_1 = !WE;
P1_q_a[10]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[10]_PORT_A_data_out = MEMORY(P1_q_a[10]_PORT_A_data_in_reg, P1_q_a[10]_PORT_B_data_in_reg, P1_q_a[10]_PORT_A_address_reg, P1_q_a[10]_PORT_B_address_reg, P1_q_a[10]_PORT_A_write_enable_reg, P1_q_a[10]_PORT_B_write_enable_reg, , , P1_q_a[10]_clock_0, P1_q_a[10]_clock_1, P1_q_a[10]_clock_enable_0, , , );
P1_q_a[10]_PORT_A_data_out_reg = DFFE(P1_q_a[10]_PORT_A_data_out, P1_q_a[10]_clock_0, , , P1_q_a[10]_clock_enable_0);
P1_q_a[10] = P1_q_a[10]_PORT_A_data_out_reg[0];


--E1L23 is MUX:inst10|O1~515
E1L23 = P1_q_a[10] & (CS # !Addr[0]);


--P1_q_a[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[9]_PORT_A_data_in = VCC;
P1_q_a[9]_PORT_A_data_in_reg = DFFE(P1_q_a[9]_PORT_A_data_in, P1_q_a[9]_clock_0, , , P1_q_a[9]_clock_enable_0);
P1_q_a[9]_PORT_B_data_in = A1L29;
P1_q_a[9]_PORT_B_data_in_reg = DFFE(P1_q_a[9]_PORT_B_data_in, P1_q_a[9]_clock_1, , , );
P1_q_a[9]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[9]_PORT_A_address_reg = DFFE(P1_q_a[9]_PORT_A_address, P1_q_a[9]_clock_0, , , P1_q_a[9]_clock_enable_0);
P1_q_a[9]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[9]_PORT_B_address_reg = DFFE(P1_q_a[9]_PORT_B_address, P1_q_a[9]_clock_1, , , );
P1_q_a[9]_PORT_A_write_enable = GND;
P1_q_a[9]_PORT_A_write_enable_reg = DFFE(P1_q_a[9]_PORT_A_write_enable, P1_q_a[9]_clock_0, , , P1_q_a[9]_clock_enable_0);
P1_q_a[9]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[9]_PORT_B_write_enable_reg = DFFE(P1_q_a[9]_PORT_B_write_enable, P1_q_a[9]_clock_1, , , );
P1_q_a[9]_clock_0 = !RE;
P1_q_a[9]_clock_1 = !WE;
P1_q_a[9]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[9]_PORT_A_data_out = MEMORY(P1_q_a[9]_PORT_A_data_in_reg, P1_q_a[9]_PORT_B_data_in_reg, P1_q_a[9]_PORT_A_address_reg, P1_q_a[9]_PORT_B_address_reg, P1_q_a[9]_PORT_A_write_enable_reg, P1_q_a[9]_PORT_B_write_enable_reg, , , P1_q_a[9]_clock_0, P1_q_a[9]_clock_1, P1_q_a[9]_clock_enable_0, , , );
P1_q_a[9]_PORT_A_data_out_reg = DFFE(P1_q_a[9]_PORT_A_data_out, P1_q_a[9]_clock_0, , , P1_q_a[9]_clock_enable_0);
P1_q_a[9] = P1_q_a[9]_PORT_A_data_out_reg[0];


--E1L24 is MUX:inst10|O1~516
E1L24 = P1_q_a[9] & (CS # !Addr[0]);


--P1_q_a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[8]_PORT_A_data_in = VCC;
P1_q_a[8]_PORT_A_data_in_reg = DFFE(P1_q_a[8]_PORT_A_data_in, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_data_in = A1L30;
P1_q_a[8]_PORT_B_data_in_reg = DFFE(P1_q_a[8]_PORT_B_data_in, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[8]_PORT_A_address_reg = DFFE(P1_q_a[8]_PORT_A_address, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[8]_PORT_B_address_reg = DFFE(P1_q_a[8]_PORT_B_address, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_write_enable = GND;
P1_q_a[8]_PORT_A_write_enable_reg = DFFE(P1_q_a[8]_PORT_A_write_enable, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[8]_PORT_B_write_enable_reg = DFFE(P1_q_a[8]_PORT_B_write_enable, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_clock_0 = !RE;
P1_q_a[8]_clock_1 = !WE;
P1_q_a[8]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[8]_PORT_A_data_out = MEMORY(P1_q_a[8]_PORT_A_data_in_reg, P1_q_a[8]_PORT_B_data_in_reg, P1_q_a[8]_PORT_A_address_reg, P1_q_a[8]_PORT_B_address_reg, P1_q_a[8]_PORT_A_write_enable_reg, P1_q_a[8]_PORT_B_write_enable_reg, , , P1_q_a[8]_clock_0, P1_q_a[8]_clock_1, P1_q_a[8]_clock_enable_0, , , );
P1_q_a[8]_PORT_A_data_out_reg = DFFE(P1_q_a[8]_PORT_A_data_out, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8] = P1_q_a[8]_PORT_A_data_out_reg[0];


--E1L25 is MUX:inst10|O1~517
E1L25 = P1_q_a[8] & (CS # !Addr[0]);


--P1_q_a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[7]_PORT_A_data_in = VCC;
P1_q_a[7]_PORT_A_data_in_reg = DFFE(P1_q_a[7]_PORT_A_data_in, P1_q_a[7]_clock_0, , , P1_q_a[7]_clock_enable_0);
P1_q_a[7]_PORT_B_data_in = A1L31;
P1_q_a[7]_PORT_B_data_in_reg = DFFE(P1_q_a[7]_PORT_B_data_in, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[7]_PORT_A_address_reg = DFFE(P1_q_a[7]_PORT_A_address, P1_q_a[7]_clock_0, , , P1_q_a[7]_clock_enable_0);
P1_q_a[7]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[7]_PORT_B_address_reg = DFFE(P1_q_a[7]_PORT_B_address, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_write_enable = GND;
P1_q_a[7]_PORT_A_write_enable_reg = DFFE(P1_q_a[7]_PORT_A_write_enable, P1_q_a[7]_clock_0, , , P1_q_a[7]_clock_enable_0);
P1_q_a[7]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[7]_PORT_B_write_enable_reg = DFFE(P1_q_a[7]_PORT_B_write_enable, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_clock_0 = !RE;
P1_q_a[7]_clock_1 = !WE;
P1_q_a[7]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[7]_PORT_A_data_out = MEMORY(P1_q_a[7]_PORT_A_data_in_reg, P1_q_a[7]_PORT_B_data_in_reg, P1_q_a[7]_PORT_A_address_reg, P1_q_a[7]_PORT_B_address_reg, P1_q_a[7]_PORT_A_write_enable_reg, P1_q_a[7]_PORT_B_write_enable_reg, , , P1_q_a[7]_clock_0, P1_q_a[7]_clock_1, P1_q_a[7]_clock_enable_0, , , );
P1_q_a[7]_PORT_A_data_out_reg = DFFE(P1_q_a[7]_PORT_A_data_out, P1_q_a[7]_clock_0, , , P1_q_a[7]_clock_enable_0);
P1_q_a[7] = P1_q_a[7]_PORT_A_data_out_reg[0];


--E1L26 is MUX:inst10|O1~518
E1L26 = P1_q_a[7] & (CS # !Addr[0]);


--P1_q_a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[6]_PORT_A_data_in = VCC;
P1_q_a[6]_PORT_A_data_in_reg = DFFE(P1_q_a[6]_PORT_A_data_in, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_data_in = A1L32;
P1_q_a[6]_PORT_B_data_in_reg = DFFE(P1_q_a[6]_PORT_B_data_in, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[6]_PORT_A_address_reg = DFFE(P1_q_a[6]_PORT_A_address, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[6]_PORT_B_address_reg = DFFE(P1_q_a[6]_PORT_B_address, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_write_enable = GND;
P1_q_a[6]_PORT_A_write_enable_reg = DFFE(P1_q_a[6]_PORT_A_write_enable, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[6]_PORT_B_write_enable_reg = DFFE(P1_q_a[6]_PORT_B_write_enable, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_clock_0 = !RE;
P1_q_a[6]_clock_1 = !WE;
P1_q_a[6]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[6]_PORT_A_data_out = MEMORY(P1_q_a[6]_PORT_A_data_in_reg, P1_q_a[6]_PORT_B_data_in_reg, P1_q_a[6]_PORT_A_address_reg, P1_q_a[6]_PORT_B_address_reg, P1_q_a[6]_PORT_A_write_enable_reg, P1_q_a[6]_PORT_B_write_enable_reg, , , P1_q_a[6]_clock_0, P1_q_a[6]_clock_1, P1_q_a[6]_clock_enable_0, , , );
P1_q_a[6]_PORT_A_data_out_reg = DFFE(P1_q_a[6]_PORT_A_data_out, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6] = P1_q_a[6]_PORT_A_data_out_reg[0];


--E1L27 is MUX:inst10|O1~519
E1L27 = P1_q_a[6] & (CS # !Addr[0]);


--P1_q_a[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[5]_PORT_A_data_in = VCC;
P1_q_a[5]_PORT_A_data_in_reg = DFFE(P1_q_a[5]_PORT_A_data_in, P1_q_a[5]_clock_0, , , P1_q_a[5]_clock_enable_0);
P1_q_a[5]_PORT_B_data_in = A1L33;
P1_q_a[5]_PORT_B_data_in_reg = DFFE(P1_q_a[5]_PORT_B_data_in, P1_q_a[5]_clock_1, , , );
P1_q_a[5]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[5]_PORT_A_address_reg = DFFE(P1_q_a[5]_PORT_A_address, P1_q_a[5]_clock_0, , , P1_q_a[5]_clock_enable_0);
P1_q_a[5]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[5]_PORT_B_address_reg = DFFE(P1_q_a[5]_PORT_B_address, P1_q_a[5]_clock_1, , , );
P1_q_a[5]_PORT_A_write_enable = GND;
P1_q_a[5]_PORT_A_write_enable_reg = DFFE(P1_q_a[5]_PORT_A_write_enable, P1_q_a[5]_clock_0, , , P1_q_a[5]_clock_enable_0);
P1_q_a[5]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[5]_PORT_B_write_enable_reg = DFFE(P1_q_a[5]_PORT_B_write_enable, P1_q_a[5]_clock_1, , , );
P1_q_a[5]_clock_0 = !RE;
P1_q_a[5]_clock_1 = !WE;
P1_q_a[5]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[5]_PORT_A_data_out = MEMORY(P1_q_a[5]_PORT_A_data_in_reg, P1_q_a[5]_PORT_B_data_in_reg, P1_q_a[5]_PORT_A_address_reg, P1_q_a[5]_PORT_B_address_reg, P1_q_a[5]_PORT_A_write_enable_reg, P1_q_a[5]_PORT_B_write_enable_reg, , , P1_q_a[5]_clock_0, P1_q_a[5]_clock_1, P1_q_a[5]_clock_enable_0, , , );
P1_q_a[5]_PORT_A_data_out_reg = DFFE(P1_q_a[5]_PORT_A_data_out, P1_q_a[5]_clock_0, , , P1_q_a[5]_clock_enable_0);
P1_q_a[5] = P1_q_a[5]_PORT_A_data_out_reg[0];


--E1L28 is MUX:inst10|O1~520
E1L28 = P1_q_a[5] & (CS # !Addr[0]);


--P1_q_a[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[4]_PORT_A_data_in = VCC;
P1_q_a[4]_PORT_A_data_in_reg = DFFE(P1_q_a[4]_PORT_A_data_in, P1_q_a[4]_clock_0, , , P1_q_a[4]_clock_enable_0);
P1_q_a[4]_PORT_B_data_in = A1L34;
P1_q_a[4]_PORT_B_data_in_reg = DFFE(P1_q_a[4]_PORT_B_data_in, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[4]_PORT_A_address_reg = DFFE(P1_q_a[4]_PORT_A_address, P1_q_a[4]_clock_0, , , P1_q_a[4]_clock_enable_0);
P1_q_a[4]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[4]_PORT_B_address_reg = DFFE(P1_q_a[4]_PORT_B_address, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_PORT_A_write_enable = GND;
P1_q_a[4]_PORT_A_write_enable_reg = DFFE(P1_q_a[4]_PORT_A_write_enable, P1_q_a[4]_clock_0, , , P1_q_a[4]_clock_enable_0);
P1_q_a[4]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[4]_PORT_B_write_enable_reg = DFFE(P1_q_a[4]_PORT_B_write_enable, P1_q_a[4]_clock_1, , , );
P1_q_a[4]_clock_0 = !RE;
P1_q_a[4]_clock_1 = !WE;
P1_q_a[4]_clock_enable_0 = H1_valid_rdreq;