freq_divider_4.vhd

implemention of FPGA and DSP linking port, using Asynchronous mode

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Freq_Divider_4 IS
	PORT(
			CLKIN	:	IN	STD_LOGIC;
			CLKOUT	:	OUT	STD_LOGIC
		);
END Freq_Divider_4;

ARCHITECTURE ARC OF Freq_Divider_4 IS
SIGNAL COUNTER	:	STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CLKOUT_Temp	:	STD_LOGIC	:=	'0';
BEGIN
	PROCESS(CLKIN)
	BEGIN
		IF(CLKIN'EVENT AND CLKIN='1')THEN
			IF(COUNTER = "00" OR COUNTER = "01" OR COUNTER = "10")THEN
				COUNTER <= COUNTER + '1';
			ELSE
				COUNTER <= (OTHERS => '0');
			END IF;
		END IF;
	END PROCESS;
	
	PROCESS(CLKIN)
	BEGIN
		IF(CLKIN'EVENT AND CLKIN='1')THEN
			IF(COUNTER = "01" OR COUNTER = "11")THEN
				CLKOUT_Temp	<=	NOT CLKOUT_Temp;
			END IF;
		END IF;
	END PROCESS;
	
	CLKOUT	<=	CLKOUT_Temp;
	
END ARC;