mux.vhd

来自「implemention of FPGA and DSP linking por」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX IS
	PORT(
			CS	:	IN 	STD_LOGIC;
			Addr:	IN	STD_LOGIC_VECTOR(1 DOWNTO 0);
			A1	:	IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			A2	:	IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			A3	:	IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			eno	:	OUT	STD_LOGIC;
			O1	:	OUT	STD_LOGIC_VECTOR(15 DOWNTO 0)
		);
END MUX;

ARCHITECTURE ARC OF MUX IS
BEGIN
	O1 <= A1 WHEN CS='0' AND Addr="11" ELSE
		  A2 WHEN CS='0' AND Addr="01" ELSE
		  A3 WHEN CS='0' AND Addr="10" ELSE
		  NULL;
	eno <= '1' WHEN CS='0' AND Addr="10" ELSE
		  '0';	
END ARC;