mobile_sdram.v

基于 MAXII 的CPLD 对mobil dram 的读写操作

/***************************************************************************************************************
* MOBILE SDRAM
***************************************************************************************************************/
 module mobile_sdram(sd_clk, sd_cke, sd_csn, sd_casn, sd_rasn, sd_wen, ldqm, udqm, sd_ba, sd_a,
  sd_data, clk, rst, cmd, data, addr);

/***************************************MOBILE SDRAM INPUTS******************************************************
	sd_clk								sdram clock
	sd_cke								sdram clock enable
	sd_csn, sd_casn, sd_rasn, sd_wen	sdram command signals
	ldqm, udqm							sdram data masking signals
 	[1:0] sd_ba							sdram bank address
	[12:0] sd_a							sdram row/column(depending on state) address
	[4:0] pr_state, nxt_state			indicate the states of operation 
****************************************************************************************************************/
	
	
/***************************************MICRO-PROCESSOR OUTPUTS*************************************************
	
	clk									clock
	rst									reset
	ds									drive strength
	[3:0] cmd							command
	[23:0] addr							address
	
****************************************************************************************************************/

  output sd_clk, sd_cke, sd_csn, sd_casn, sd_rasn, sd_wen, ldqm, udqm;
  output [1:0] sd_ba;
  output [12:0] sd_a;

  input clk, rst;
  input [3:0] cmd;
  input [23:0] addr;

  inout  [15:0] data;
  inout  [15:0] sd_data;
 
 
  wire [1:0] cas_cnt;
  wire [3:0] read_cnt, write_cnt; 

 
  reg cas_rst, read_rst, write_rst, cas_cnt_en, read_cnt_en, write_cnt_en;
  reg [4:0] pr_state, nxt_state;
  reg sd_cke, sd_csn, sd_casn, sd_rasn, sd_wen;
  reg fsm_cke, fsm_csn, fsm_casn, fsm_rasn, fsm_wen; 
  reg rw;
  reg [3:0]b_len;
  reg [1:0]cas;

 addr_gen address     (.clk(clk), .addr(addr), .pr_state(pr_state), .ba(sd_ba), .a(sd_a));
						
 upcount_2 cas_cntr   (.clk(clk), .reset(cas_rst), .count_en(cas_cnt_en), .count(cas_cnt));
 upcount_4 read_cntr  (.clk(clk), .reset(read_rst), .count_en(read_cnt_en), .count(read_cnt));
 upcount_4 write_cntr (.clk(clk), .reset(write_rst), .count_en(write_cnt_en), .count(write_cnt));



//micro-processor commands
 parameter inhibit	       = 4'b1100;
 parameter read		 	   = 4'b0001;
 parameter write	   	   = 4'b0010;
 parameter power_down  	   = 4'b0011;
 parameter precharge	   = 4'b0100;
 parameter refresh		   = 4'b0101;
 parameter dpd			   = 4'b0110;
 parameter lmr			   = 4'b1000;
 parameter dpd_exit	 	   = 4'b1010;
 parameter power_down_exit = 4'b1011;
 parameter nop			   = 4'b0000; 


//finite_state_machine states 
 parameter idle_st		   = 5'b00000;
 parameter active_read_st  = 5'b00001;
 parameter t_rcd_read_st   = 5'b00010;
 parameter read_st		   = 5'b00011;
 parameter write_st		   = 5'b00100;
 parameter cas_st		   = 5'b00101;
 parameter read_data_st    = 5'b00110;
 parameter dpd_st		   = 5'b00111;
 parameter refresh_st	   = 5'b01000;
 parameter precharge_st	   = 5'b01001;
 parameter lmr_st		   = 5'b01010;               //loads emr or mr depending upon the value BA0 and BA1
 parameter t_wr_st		   = 5'b01011;
 parameter t_rp_st		   = 5'b01100;
 parameter write_data_st   = 5'b01101;
 parameter power_down_st   = 5'b01110;
 parameter active_write_st = 5'b11111;
 parameter t_rcd_write_st  = 5'b10000; 

assign sd_clk = clk;

//data masking is not required in this model as the write burst is never terminated before completion 
assign ldqm = 0;
assign udqm = 0;

bufif1 buffer16 [15:0] (sd_data,data,rw);
bufif0 buf16 [15:0] (data, sd_data ,rw);

//assign pr_state to nxt_state at positive clock edge
always @ (posedge clk, posedge rst)  
begin

		if(rst == 1)
		begin
		sd_cke  = 1;
		sd_csn  = 0;
		sd_casn = 1;
		sd_rasn = 1;
		sd_wen  = 1;
		end

		else
		begin
		pr_state = nxt_state;
		
		sd_cke   = fsm_cke;
		sd_csn   = fsm_csn;
		sd_casn  = fsm_casn;
		sd_rasn  = fsm_rasn;
		sd_wen   = fsm_wen;

		if(pr_state == read_data_st) 	    rw = 0;
		else if (pr_state == write_data_st) rw = 1;
		end
end

// decides the next state depending on micro-processor commands
always @ (posedge rst,posedge clk)
 begin

 if(rst==1) nxt_state = idle_st;

else
begin

 case (pr_state)
 idle_st:
 begin
    
            fsm_cke      = 1 ; 
            fsm_csn      = 0 ;
			fsm_casn     = 1 ;
			fsm_rasn     = 1 ;
			fsm_wen      = 1 ;
			read_cnt_en  = 0;
			write_cnt_en = 0;
			
			if (cmd == inhibit)
			 fsm_csn = 1 ;
			
			else if (cmd == lmr) 	nxt_state= lmr_st;

			else if (cmd==refresh)      nxt_state = refresh_st;

			else if (cmd==precharge) 	nxt_state = precharge_st;

			else if (cmd==dpd)		nxt_state = dpd_st;

			else if (cmd==read)		nxt_state = active_read_st;	
			
			else if (cmd==write)		nxt_state = active_write_st;

			else if (cmd==power_down)	nxt_state = power_down_st;

			else if (cmd==nop)		nxt_state = idle_st;
			
			else nxt_state = idle_st;

end 

lmr_st:
 begin
            
			fsm_cke  = 1 ;
			fsm_csn  = 0 ; 
			fsm_casn = 0 ;
			fsm_rasn = 0 ;
			fsm_wen  = 0 ;
			
			nxt_state = idle_st; 			

if(addr[23:22]==2'b00)              
begin

  case(addr[2:0])                      //converts 2 bit burst length entered by the user into 4 bit format as required by the sdram

	2'b00:
			b_len = 4'b0001;
	2'b01:
			b_len = 4'b0010;
	2'b10: 
			b_len = 4'b0100;
	2'b11:
			b_len = 4'b1000;
	default:
			b_len = 4'b0001;
  endcase

  cas = addr[5:4];
end

else
begin
end        
end

			
 refresh_st:
 begin
            
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 0 ;
			fsm_rasn  = 0 ;
			fsm_wen   = 1 ;
			
            nxt_state = idle_st; 

 end

 precharge_st:
 begin
            
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 0 ;  
			fsm_wen   = 0 ;
			
            nxt_state = idle_st; 
end




 power_down_st:                        
 begin			
            
         	fsm_cke   = 0 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 1 ;	
			
			if(cmd == power_down_exit)		nxt_state = idle_st;
 end


 dpd_st:
 begin

			fsm_cke   = 0 ;  
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 0 ;	
			
			if(cmd == dpd_exit)		nxt_state = idle_st;
			
end

 active_read_st:
 begin

            fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 0 ;
			fsm_wen   = 1 ;
			
			nxt_state = t_rcd_read_st;
	
		
 end
 t_rcd_read_st:
begin
			
		
			nxt_state = read_st;
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 0 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 1 ;
			
			
 end


 read_st:
begin
         
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 1 ;
			cas_rst   = 1 ;
			read_rst  = 1 ;			
						
			if(cas == 2'b01)
			 nxt_state = read_data_st;
			else
			begin
			 nxt_state = cas_st;
			 cas_rst = 0; 			 
			end
end


 cas_st:
 begin
        
			fsm_cke    = 1 ;
			fsm_csn    = 0 ; 
			fsm_casn   = 1 ;
			fsm_rasn   = 1 ;
			fsm_wen    = 1 ;
			
			cas_cnt_en = 1;
		
			          
			
			if(cas_cnt+2'b10 == cas)
			     nxt_state = read_data_st;
			
		
 end



 read_data_st:
 begin
         
			fsm_cke      = 1 ;
			fsm_csn      = 0 ; 
			fsm_casn     = 1 ;
			fsm_rasn     = 1 ;
			fsm_wen      = 1 ;
			
			cas_cnt_en   = 0;
			read_rst     = 0 ;
			read_cnt_en  = 1 ;
			
			if(cas == 2'b01)
			  if(read_cnt+4'b0001 == b_len)
			begin
			     nxt_state = idle_st;
		         

 			end

			else
			
			if(read_cnt == b_len)
			   begin
			nxt_state = idle_st;
	
 end
end





 active_write_st:
 begin
     
			nxt_state = t_rcd_write_st;
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 0 ;
			fsm_wen   = 1 ;

 end



 t_rcd_write_st:
begin
			

			nxt_state = write_st;
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 0 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 0 ;
			
			
 end

 write_st:
 begin
     
			fsm_cke  = 1 ;
			fsm_csn  = 0 ; 
			fsm_casn = 1 ;
			fsm_rasn = 1 ;
			fsm_wen  = 1 ;

			write_rst = 1 ;
			nxt_state = write_data_st;
 end


 write_data_st:
 begin
         
			fsm_cke      = 1 ;
			fsm_csn      = 0 ; 
			fsm_casn     = 1 ;
			fsm_rasn     = 1 ;
			fsm_wen      = 1 ;
			
			write_rst    = 0;
			write_cnt_en = 1;
			

			if(write_cnt+4'b0001 == b_len)
			   nxt_state = t_wr_st;
			

 end



 t_wr_st:
 begin
    
			fsm_cke   = 1 ;
			fsm_csn   = 0 ; 
			fsm_casn  = 1 ;
			fsm_rasn  = 1 ;
			fsm_wen   = 1 ;
			
			nxt_state = t_rp_st;
 end


 t_rp_st:
 begin
      
			fsm_cke  = 1 ;
			fsm_csn  = 0 ; 
			fsm_casn = 1 ;
			fsm_rasn = 1 ;
			fsm_wen  = 1 ;

			nxt_state = idle_st;
			
			 end

default:
begin
            nxt_state = idle_st;


end
  
      
endcase
end
end
endmodule
/***************************************************END*******************************************************/