📄 top.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\4_monday\top.rpt
top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
121 - - - 17 OUTPUT 0 1 0 0 A
117 - - - 08 OUTPUT 0 1 0 0 B
132 - - - 26 OUTPUT 0 1 0 0 C
119 - - - 13 OUTPUT 0 1 0 0 D
128 - - - 19 OUTPUT 0 0 0 0 dot
112 - - - 04 OUTPUT 0 1 0 0 E
131 - - - 23 OUTPUT 0 1 0 0 F
110 - - - 02 OUTPUT 0 1 0 0 GG
88 - - D -- OUTPUT 0 1 0 0 G1
114 - - - 06 OUTPUT 0 1 0 0 G2
98 - - B -- OUTPUT 0 1 0 0 G3
90 - - D -- OUTPUT 0 1 0 0 G4
87 - - E -- OUTPUT 0 1 0 0 G5
89 - - D -- OUTPUT 0 1 0 0 G6
95 - - C -- OUTPUT 0 1 0 0 G7
99 - - B -- OUTPUT 0 1 0 0 G8
36 - - - 36 OUTPUT 0 1 0 0 G9
33 - - F -- OUTPUT 0 1 0 0 G10
29 - - E -- OUTPUT 0 1 0 0 G11
31 - - F -- OUTPUT 0 1 0 0 G12
30 - - F -- OUTPUT 0 1 0 0 G13
63 - - - 11 OUTPUT 0 1 0 0 G14
68 - - - 07 OUTPUT 0 1 0 0 G15
73 - - - 01 OUTPUT 0 1 0 0 G16
111 - - - 03 OUTPUT 0 1 0 0 maingreen
120 - - - 14 OUTPUT 0 1 0 0 mainred
116 - - - 07 OUTPUT 0 1 0 0 mainyellow
138 - - - 31 OUTPUT 0 1 0 0 out0
141 - - - 33 OUTPUT 0 1 0 0 out1
142 - - - 34 OUTPUT 0 1 0 0 out2
136 - - - 30 OUTPUT 0 1 0 0 out3
140 - - - 32 OUTPUT 0 1 0 0 out4
133 - - - 28 OUTPUT 0 1 0 0 out5
60 - - - 15 OUTPUT 0 1 0 0 ROW3
48 - - - 24 OUTPUT 0 1 0 0 ROW4
46 - - - 27 OUTPUT 0 1 0 0 ROW5
43 - - - 30 OUTPUT 0 1 0 0 ROW6
41 - - - 31 OUTPUT 0 1 0 0 ROW7
38 - - - 34 OUTPUT 0 1 0 0 ROW8
51 - - - 20 OUTPUT 0 1 0 0 RO1
59 - - - 16 OUTPUT 0 1 0 0 RO2
80 - - F -- OUTPUT 0 1 0 0 R1
100 - - A -- OUTPUT 0 1 0 0 R2
102 - - A -- OUTPUT 0 1 0 0 R3
96 - - C -- OUTPUT 0 1 0 0 R4
83 - - E -- OUTPUT 0 1 0 0 R5
91 - - D -- OUTPUT 0 1 0 0 R6
97 - - C -- OUTPUT 0 1 0 0 R7
101 - - A -- OUTPUT 0 1 0 0 R8
32 - - F -- OUTPUT 0 1 0 0 R9
27 - - E -- OUTPUT 0 1 0 0 R10
65 - - - 09 OUTPUT 0 1 0 0 R11
81 - - F -- OUTPUT 0 1 0 0 R12
28 - - E -- OUTPUT 0 1 0 0 R13
70 - - - 05 OUTPUT 0 1 0 0 R14
79 - - F -- OUTPUT 0 1 0 0 R15
78 - - F -- OUTPUT 0 1 0 0 R16
130 - - - 22 OUTPUT 0 0 0 0 4th
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\4_monday\top.rpt
top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 30 DFFE + 0 2 0 8 |counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 7 - B 30 DFFE + 0 1 0 9 |counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 1 - B 19 DFFE + 0 0 0 10 |counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|counter0:82|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 6 - C 32 DFFE + 0 1 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QH (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:1)
- 4 - C 32 DFFE + 0 3 0 1 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QG (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:2)
- 3 - C 32 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QF (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:3)
- 1 - C 32 DFFE + 0 1 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QE (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:4)
- 4 - F 29 DFFE + 0 3 0 1 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QD (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:5)
- 1 - F 34 DFFE + 0 2 0 8 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 4 - F 34 DFFE + 0 1 0 9 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 2 - F 34 DFFE + 0 0 0 10 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 6 - F 29 AND2 0 4 0 4 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:291
- 5 - C 32 AND2 0 4 0 4 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c0|:297
- 1 - C 10 DFFE + 0 3 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QH (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:1)
- 8 - C 10 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QG (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:2)
- 7 - C 10 DFFE + 0 1 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QF (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:3)
- 5 - C 10 DFFE + 0 3 0 1 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QE (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:4)
- 4 - C 10 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QD (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:5)
- 3 - C 10 DFFE + 0 1 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QC (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:6)
- 8 - C 32 DFFE + 0 3 0 1 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QB (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:7)
- 7 - C 32 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|QA (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:8)
- 2 - C 32 AND2 0 4 0 4 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:287
- 6 - C 10 AND2 0 4 0 4 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:293
- 2 - C 10 AND2 0 4 0 4 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c1|:299
- 4 - C 02 DFFE + 0 3 0 20 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QF (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:3)
- 8 - C 02 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QE (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:4)
- 7 - C 02 DFFE + 0 1 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QD (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:5)
- 5 - C 02 DFFE + 0 3 0 1 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QC (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:6)
- 3 - C 02 DFFE + 0 2 0 2 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QB (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:7)
- 1 - C 02 DFFE + 0 1 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|QA (|counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:8)
- 6 - C 02 AND2 0 4 0 3 |counter_1:1|lpm_counter:lpm_counter_component|f8count:p8c2|:289
- 2 - F 03 DFFE 0 1 0 22 |count3:146|count0
- 1 - F 03 DFFE 0 4 0 16 |count3:146|count1
- 6 - F 06 DFFE 0 4 0 14 |count3:146|count2
- 5 - F 06 DFFE 0 3 0 10 |count3:146|COUNT3
- 3 - F 06 DFFE 0 4 0 9 |count3:146|count4
- 7 - F 06 OR2 s 0 2 0 11 |count3:146|~45~1
- 2 - F 14 OR2 ! 0 2 0 8 |count3:146|:52
- 1 - F 06 OR2 ! 0 2 0 9 |count3:146|:56
- 8 - F 05 DFFE 1 1 0 2 |count3600s:151|COUNT3600S0
- 7 - F 05 DFFE 0 3 0 1 |count3600s:151|COUNT3600S1
- 7 - C 07 DFFE 0 3 0 2 |count3600s:151|COUNT3600S2
- 8 - C 07 DFFE 0 4 0 1 |count3600s:151|COUNT3600S3
- 6 - C 07 DFFE 0 3 0 3 |count3600s:151|COUNT3600S4
- 5 - C 07 DFFE 0 4 0 2 |count3600s:151|COUNT3600S5
- 4 - F 05 DFFE 0 3 0 3 |count3600s:151|COUNT3600S6
- 8 - C 18 DFFE 0 4 0 2 |count3600s:151|COUNT3600S7
- 7 - C 18 DFFE 0 3 0 3 |count3600s:151|COUNT3600S8
- 6 - C 18 DFFE 0 4 0 2 |count3600s:151|COUNT3600S9
- 5 - C 18 DFFE 0 3 0 2 |count3600s:151|COUNT3600S10
- 4 - C 18 DFFE 0 4 0 1 |count3600s:151|COUNT3600S11
- 2 - C 07 OR2 s 0 4 0 1 |count3600s:151|~59~1
- 2 - C 18 OR2 s 0 4 0 1 |count3600s:151|~59~2
- 4 - C 07 OR2 1 3 0 12 |count3600s:151|:65
- 1 - F 05 AND2 0 2 0 3 |count3600s:151|:72
- 3 - C 07 AND2 0 3 0 4 |count3600s:151|:80
- 1 - C 07 AND2 0 3 0 3 |count3600s:151|:88
- 1 - C 18 AND2 0 3 0 3 |count3600s:151|:96
- 3 - C 18 AND2 0 3 0 2 |count3600s:151|:104
- 2 - F 32 AND2 0 4 1 4 |digselector:138|:69
- 6 - F 34 AND2 0 4 1 1 |digselector:138|:81
- 8 - F 34 AND2 0 4 1 4 |digselector:138|:97
- 6 - F 28 OR2 ! 0 4 0 1 |digselector:138|:98
- 1 - F 29 AND2 0 4 1 1 |digselector:138|:114
- 5 - F 29 OR2 ! 0 4 0 1 |digselector:138|:115
- 8 - F 32 AND2 ! 0 3 1 4 |digselector:138|:127
- 7 - F 34 OR2 s ! 0 4 0 1 |digselector:138|~137~1
- 8 - F 09 OR2 0 4 0 7 |digselector:138|:137
- 5 - F 14 OR2 s 0 4 0 1 |digselector:138|~140~1
- 3 - F 14 OR2 ! 0 4 0 7 |digselector:138|:140
- 6 - F 12 AND2 s 0 4 0 1 |digselector:138|~144~1
- 1 - F 28 AND2 ! 0 3 1 2 |digselector:138|:144
- 5 - F 28 OR2 ! 0 4 0 1 |digselector:138|:147
- 2 - F 28 OR2 s 0 4 0 1 |digselector:138|~148~1
- 7 - F 29 OR2 s 0 4 0 1 |digselector:138|~148~2
- 3 - F 29 OR2 ! 0 4 0 7 |digselector:138|:148
- 2 - F 01 OR2 s 0 2 0 1 |digselector:138|~151~1
- 5 - F 01 OR2 s 0 3 0 1 |digselector:138|~151~2
- 6 - F 01 OR2 s 0 4 0 1 |digselector:138|~151~3
- 7 - F 01 OR2 ! 0 4 0 7 |digselector:138|:151
- 5 - F 04 OR2 0 4 1 0 |greenswitch:5|:36
- 2 - C 02 OR2 0 3 0 5 |modifier:132|:34
- 2 - F 05 DFFE 1 1 0 13 |mycount3:150|count0
- 3 - F 09 DFFE 0 3 0 15 |mycount3:150|count1
- 6 - F 09 DFFE 0 4 0 13 |mycount3:150|count2
- 6 - F 05 DFFE 1 3 0 16 |mycount3:150|count3
- 5 - F 05 DFFE 0 4 0 12 |mycount3:150|count4
- 1 - F 02 OR2 s 0 2 0 9 |mycount3:150|~46~1
- 3 - F 01 AND2 s 0 4 0 1 |mycount3:150|~46~2
- 3 - F 05 OR2 1 2 0 3 |mycount3:150|:51
- 1 - F 09 OR2 ! 0 3 0 7 |mycount3:150|:62
- 4 - B 15 AND2 s 0 3 0 5 |myexpand:141|~85~1
- 6 - B 30 AND2 s 0 3 0 3 |myexpand:141|~262~1
- 5 - F 23 OR2 0 4 0 3 |myexpand:141|:262
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -