📄 top.rpt
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R R o o o o R o R C o C n R n R l C R r R
V V u u u G u V u V C u 4 G d I C 1 G G V r V l C V e V
E E t t t N t E t E I t t N o N L 2 N N E e E o I G E e G E
D D 2 1 4 D 0 D 3 D O 5 C F h D t T R 5 D D D A d D D B w O 2 D E n G D
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/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | R3
RESERVED | 8 101 | R8
RESERVED | 9 100 | R2
RESERVED | 10 99 | G8
RESERVED | 11 98 | G3
RESERVED | 12 97 | R7
RESERVED | 13 96 | R4
RESERVED | 14 95 | G7
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | R6
RESERVED | 19 EP1K30TC144-1 90 | G4
RESERVED | 20 89 | G6
RESERVED | 21 88 | G1
RESERVED | 22 87 | G5
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | R5
R10 | 27 82 | RESERVED
R13 | 28 81 | R12
G11 | 29 80 | R1
G13 | 30 79 | R15
G12 | 31 78 | R16
R9 | 32 77 | ^MSEL0
G10 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
G9 | 36 73 | G16
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R V R G V G C G G G R R V R G R R G K G R R V R
E O E N O E O E C O E O E C O N C N L N N N O O C E 1 E 1 N E 1 E 1 C E
S W S D W S W S C W S W S C 1 D C D K D D D 2 W C S 4 S 1 D Y 5 S 4 C S
E 8 E 7 E 6 E I 5 E 4 E I _ I _ 3 I E E E I E
R R R R O R R N C N C O R R R O R
V V V V V V T K K V V V V
E E E E E E L L E E E E
D D D D D D K K D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\4_monday\top.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A14 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A18 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B12 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B15 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
B23 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B28 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B30 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 2/22( 9%)
C2 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
C7 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C10 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C32 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D5 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
D8 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
D24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D26 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
E2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
E12 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
F1 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
F2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
F3 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 6/22( 27%)
F4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
F5 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 7/22( 31%)
F6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 2/22( 9%)
F7 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
F8 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
F9 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 11/22( 50%)
F10 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
F12 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 17/22( 77%)
F14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
F15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
F17 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
F18 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
F20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
F28 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
F29 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 14/22( 63%)
F31 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 0/2 0/2 13/22( 59%)
F32 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 0/2 0/2 12/22( 54%)
F33 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
F34 7/ 8( 87%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
F36 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 59/96 ( 61%)
Total logic cells used: 292/1728 ( 16%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 986/6912 ( 14%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 58
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 292
Total flipflops required: 48
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 130/1728 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 1 0 0 0 1 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
B: 1 0 0 0 0 0 0 0 0 0 0 8 0 0 8 0 0 0 0 1 0 0 0 7 0 0 0 0 1 0 8 0 0 0 0 0 0 34/0
C: 0 8 0 0 0 0 8 0 0 8 0 0 0 0 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 41/0
D: 0 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 18/0
E: 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
F: 8 8 8 8 8 8 8 8 8 8 0 8 0 8 1 8 8 8 0 0 1 0 0 8 0 0 0 0 6 7 0 8 8 4 7 0 8 178/0
Total: 9 24 9 8 16 8 17 16 8 16 0 24 0 10 10 8 8 17 0 1 1 0 0 15 1 0 1 0 7 7 8 8 16 4 7 0 8 292/0
Device-Specific Information: e:\4_monday\top.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 CLKIN
126 - - - -- INPUT ^ 0 0 0 5 CLR
67 - - - 08 INPUT ^ 0 0 0 1 KEY
125 - - - -- INPUT G ^ 0 0 0 0 pin125
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
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